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synth-layout-v1

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eda
chip-design
vlsi
synthesis
place-and-route
drc
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  1. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/cell_library.json +1 -0
  2. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/cell_neighborhoods.json +0 -0
  3. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/cell_pin_locations.json +1 -0
  4. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/deepgate.json +1 -0
  5. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/drc_labels.json +1 -0
  6. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/geometry_patches.json +0 -0
  7. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/instance_placement.json +1 -0
  8. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/ir_drop_vdd.json +1 -0
  9. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/mesoscale_blocks.json +1 -0
  10. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/net_connectivity.json +1 -0
  11. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/net_wire_info.json +1 -0
  12. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/physics_labels.json +0 -0
  13. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/pin_access.json +1 -0
  14. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/power_grid.json +1 -0
  15. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/power_summary.json +1 -0
  16. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/timing_contexts.json +1 -0
  17. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/timing_paths_detailed.json +0 -0
  18. mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/trajectory_snapshots.json +1 -0
  19. mul_w8_unsigned_p0_sky130_500mhz/flow/design_only.cdl.gz +3 -0
  20. mul_w8_unsigned_p0_sky130_500mhz/flow/flow_log.txt +94 -0
  21. mul_w8_unsigned_p0_sky130_500mhz/flow/klayout_lvs.log +763 -0
  22. mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_cleaned.gds.gz +3 -0
  23. mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_deck_patched.lylvs +295 -0
  24. mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_extracted.cir +0 -0
  25. mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_reference.cdl.gz +3 -0
  26. mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_report.lyrdb +2710 -0
  27. mul_w8_unsigned_p0_sky130_500mhz/flow/mul_w8_unsigned_p0.gds.gz +3 -0
  28. mul_w8_unsigned_p0_sky130_500mhz/flow/mul_w8_unsigned_p0.spef.gz +3 -0
  29. mul_w8_unsigned_p0_sky130_500mhz/flow/output.def.gz +3 -0
  30. mul_w8_unsigned_p0_sky130_500mhz/result.json +37 -0
mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/cell_library.json ADDED
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+ [{"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__nor2_1", "area_um2": 3.7536}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__xor2_1", "area_um2": 8.7584}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__o21ai_0", "area_um2": 5.0048}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__or3_1", "area_um2": 6.256}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__a21oi_1", "area_um2": 5.0048}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__o31ai_1", "area_um2": 7.5072}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__or4_1", "area_um2": 7.5072}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__dfxtp_1", "area_um2": 20.019199}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__decap_4", "area_um2": 5.0048}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__tapvpwrvgnd_1", "area_um2": 0.0}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__clkbuf_1", "area_um2": 3.7536}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__fill_1", "area_um2": 0.0}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__fill_2", "area_um2": 0.0}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "cell_type": "sky130_fd_sc_hd__fill_4", "area_um2": 0.0}]
mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/cell_neighborhoods.json ADDED
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mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/cell_pin_locations.json ADDED
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+ [{"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_09_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "A", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 5.26}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_09_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "B", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 4.4}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_09_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "Y", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 4.656}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_09_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "VGND", "sig_type": "GROUND", "x_um": 0.001, "y_um": 4.83}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_09_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "VNB", "sig_type": "GROUND", "x_um": 0.001, "y_um": 4.375}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_09_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "VPB", "sig_type": "POWER", "x_um": 0.001, "y_um": 4.83}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_09_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "VPWR", "sig_type": "POWER", "x_um": 0.001, "y_um": 4.83}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_10_", "cell_type": "sky130_fd_sc_hd__xor2_1", "pin_name": "A", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 8.935}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_10_", "cell_type": "sky130_fd_sc_hd__xor2_1", "pin_name": "B", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 9.074}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_10_", "cell_type": "sky130_fd_sc_hd__xor2_1", "pin_name": "X", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 10.465}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_10_", "cell_type": "sky130_fd_sc_hd__xor2_1", "pin_name": "VGND", "sig_type": "GROUND", "x_um": 0.001, "y_um": 9.43}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_10_", "cell_type": "sky130_fd_sc_hd__xor2_1", "pin_name": "VNB", "sig_type": "GROUND", "x_um": 0.001, "y_um": 8.05}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_10_", "cell_type": "sky130_fd_sc_hd__xor2_1", "pin_name": "VPB", "sig_type": "POWER", "x_um": 0.001, "y_um": 9.43}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_10_", "cell_type": "sky130_fd_sc_hd__xor2_1", "pin_name": "VPWR", "sig_type": "POWER", "x_um": 0.001, "y_um": 9.43}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_11_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "A", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 6.640000000000001}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_11_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "B", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 5.78}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_11_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "Y", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 6.0360000000000005}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_11_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "VGND", "sig_type": "GROUND", "x_um": 0.001, "y_um": 6.21}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_11_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "VNB", "sig_type": "GROUND", "x_um": 0.001, "y_um": 5.755}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_11_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "VPB", "sig_type": "POWER", "x_um": 0.001, "y_um": 6.21}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_11_", "cell_type": "sky130_fd_sc_hd__nor2_1", "pin_name": "VPWR", "sig_type": "POWER", "x_um": 0.001, "y_um": 6.21}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_12_", "cell_type": "sky130_fd_sc_hd__o21ai_0", "pin_name": "A1", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 13.59}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_12_", "cell_type": "sky130_fd_sc_hd__o21ai_0", "pin_name": "A2", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 14.087}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_12_", "cell_type": "sky130_fd_sc_hd__o21ai_0", "pin_name": "B1", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 14.962}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_12_", "cell_type": "sky130_fd_sc_hd__o21ai_0", "pin_name": "Y", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 14.66}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_12_", "cell_type": "sky130_fd_sc_hd__o21ai_0", "pin_name": "VGND", "sig_type": "GROUND", "x_um": 0.001, "y_um": 14.26}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_12_", "cell_type": "sky130_fd_sc_hd__o21ai_0", "pin_name": "VNB", "sig_type": "GROUND", "x_um": 0.001, "y_um": 13.57}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_12_", "cell_type": "sky130_fd_sc_hd__o21ai_0", "pin_name": "VPB", "sig_type": "POWER", "x_um": 0.001, "y_um": 14.26}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_12_", "cell_type": "sky130_fd_sc_hd__o21ai_0", "pin_name": "VPWR", "sig_type": "POWER", "x_um": 0.001, "y_um": 14.26}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_13_", "cell_type": "sky130_fd_sc_hd__or3_1", "pin_name": "A", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 11.435}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_13_", "cell_type": "sky130_fd_sc_hd__or3_1", "pin_name": "B", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 11.26}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_13_", "cell_type": "sky130_fd_sc_hd__or3_1", "pin_name": "C", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 10.837}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_13_", "cell_type": "sky130_fd_sc_hd__or3_1", "pin_name": "X", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 12.67}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_13_", "cell_type": "sky130_fd_sc_hd__or3_1", "pin_name": "VGND", "sig_type": "GROUND", "x_um": 0.001, "y_um": 11.73}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_13_", "cell_type": "sky130_fd_sc_hd__or3_1", "pin_name": "VNB", "sig_type": "GROUND", "x_um": 0.001, "y_um": 10.805}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_13_", "cell_type": "sky130_fd_sc_hd__or3_1", "pin_name": "VPB", "sig_type": "POWER", "x_um": 0.001, "y_um": 11.73}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_13_", "cell_type": "sky130_fd_sc_hd__or3_1", "pin_name": "VPWR", "sig_type": "POWER", "x_um": 0.001, "y_um": 11.73}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_14_", "cell_type": "sky130_fd_sc_hd__a21oi_1", "pin_name": "A1", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 13.983}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_14_", "cell_type": "sky130_fd_sc_hd__a21oi_1", "pin_name": "A2", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 14.472}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_14_", "cell_type": "sky130_fd_sc_hd__a21oi_1", "pin_name": "B1", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 13.095}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_14_", "cell_type": "sky130_fd_sc_hd__a21oi_1", "pin_name": "Y", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 13.401}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_14_", "cell_type": "sky130_fd_sc_hd__a21oi_1", "pin_name": "VGND", "sig_type": "GROUND", "x_um": 0.001, "y_um": 13.8}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_14_", "cell_type": "sky130_fd_sc_hd__a21oi_1", "pin_name": "VNB", "sig_type": "GROUND", "x_um": 0.001, "y_um": 13.11}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_14_", "cell_type": "sky130_fd_sc_hd__a21oi_1", "pin_name": "VPB", "sig_type": "POWER", "x_um": 0.001, "y_um": 13.8}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_14_", "cell_type": "sky130_fd_sc_hd__a21oi_1", "pin_name": "VPWR", "sig_type": "POWER", "x_um": 0.001, "y_um": 13.8}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_15_", "cell_type": "sky130_fd_sc_hd__o31ai_1", "pin_name": "A1", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 6.245}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_15_", "cell_type": "sky130_fd_sc_hd__o31ai_1", "pin_name": "A2", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 6.812}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_15_", "cell_type": "sky130_fd_sc_hd__o31ai_1", "pin_name": "A3", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 7.501}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_15_", "cell_type": "sky130_fd_sc_hd__o31ai_1", "pin_name": "B1", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 8.482}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "_15_", "cell_type": "sky130_fd_sc_hd__o31ai_1", "pin_name": "Y", "sig_type": "SIGNAL", "x_um": 0.001, "y_um": 8.161}, {"run_id": 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mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/geometry_patches.json ADDED
The diff for this file is too large to render. See raw diff
 
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mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/net_connectivity.json ADDED
@@ -0,0 +1 @@
 
 
1
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mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/net_wire_info.json ADDED
@@ -0,0 +1 @@
 
 
1
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mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/physics_labels.json ADDED
The diff for this file is too large to render. See raw diff
 
mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/pin_access.json ADDED
@@ -0,0 +1 @@
 
 
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"sky130", "net": "VSS", "layer": "met1", "width": 0, "coords": [{"x": 14950, "y": 2720}]}]
mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/power_summary.json ADDED
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+ [{"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "instance": "__TOTAL__", "internal_mw": 4.91958e-05, "switching_mw": 2.171214e-05, "leakage_mw": 9.068234e-11, "total_mw": 7.090803e-05}]
mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/timing_contexts.json ADDED
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+ [{"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "freq_mhz": 1000, "wns_ns": null, "tns_ns": null, "utilization": 0.55, "num_instances": 659, "area_um2": 2220.0, "multi_corner": ["ff_n40C_1v95 (fast) WNS: NaN ns TNS: NaN ns [VIOLATED]", "tt_025C_1v80 (typical) WNS: NaN ns TNS: NaN ns [VIOLATED]", "ss_n40C_1v40 (slow) WNS: NaN ns TNS: NaN ns [VIOLATED]", "ff_n40C_1v95 (fast) WNS: NaN ns TNS: NaN ns [VIOLATED]", "tt_025C_1v80 (typical) WNS: NaN ns TNS: NaN ns [VIOLATED]", "ss_n40C_1v40 (slow) WNS: NaN ns TNS: NaN ns [VIOLATED]"], "power_mw": null, "drc_clean": true, "lvs_clean": true}]
mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/timing_paths_detailed.json ADDED
The diff for this file is too large to render. See raw diff
 
mul_w8_unsigned_p0_sky130_1000mhz/flow/extracted/trajectory_snapshots.json ADDED
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+ [{"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "phase": 1, "label": "Step 1/3: Synthesis", "type": "phase_start"}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "phase": 1, "cells": 244, "type": "synth_result"}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "phase": 1, "duration_s": 0.8, "type": "phase_end"}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "phase": 2, "label": "Step 2/3: Place and Route", "type": "phase_start"}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "phase": 2, "instances": 659, "utilization": 0.55, "type": "pnr_result"}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "phase": 2, "duration_s": 44.9, "type": "phase_end"}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "phase": 3, "label": "Step 3/3: GDS Generation", "type": "phase_start"}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "phase": 3, "duration_s": 57.43, "type": "phase_end"}, {"run_id": "mul_w8_unsigned_p0_sky130_1000mhz", "pdk": "sky130", "phase": 3, "signoff": "PASS", "type": "signoff_result"}]
mul_w8_unsigned_p0_sky130_500mhz/flow/design_only.cdl.gz ADDED
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+ version https://git-lfs.github.com/spec/v1
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+ oid sha256:77cf61414c132247b14cbf918186cad572f683ae3da633f4ac2b410e6aa770a0
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+ size 3547
mul_w8_unsigned_p0_sky130_500mhz/flow/flow_log.txt ADDED
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+ ╔══════════════════════════════════════════╗
2
+ ║ Zyphar Flow v1.0.0 ║
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+ ║ Complete RTL-to-GDSII Toolchain ║
4
+ ╚══════════════════════════════════════════╝
5
+
6
+ Configuration:
7
+ Input: /tmp/datagen_designs/mul_w8_unsigned_p0/mul_w8_unsigned_p0.v
8
+ Top: mul_w8_unsigned_p0
9
+ PDK: Sky130
10
+ Frequency: 500 MHz
11
+ Clock: clk
12
+ Output: /tmp/datagen_output/mul_w8_unsigned_p0_sky130_500mhz/flow
13
+
14
+ Starting flow...
15
+
16
+ === Step 1/3: Synthesis ===
17
+ Synthesis complete: 244 cells, 0.00 um^2
18
+ Wires: 231, Modules: 1
19
+ Netlist: /tmp/zyphar_netlist_1357452.v
20
+ Duration: 0.5s
21
+
22
+ --- CDC Analysis ---
23
+ No clock domain crossings detected
24
+
25
+ --- Native Re-Optimization ---
26
+ Skipped (no Liberty file provided, use --liberty)
27
+
28
+ === Step 2/3: Place and Route ===
29
+ Input netlist: /tmp/zyphar_netlist_1357452.v
30
+ PDK: Sky130, Freq: 500 MHz, Clock: clk
31
+ Utilization: 45%, Aspect ratio: 1.0, Placement density: 0.80 (auto)
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+ PDN: true, Detailed route: true, Fillers: true, Antenna: true
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+ PnR complete: 659 instances, 0.55 utilization
34
+ DEF: /tmp/zyphar_pnr_1357452.def
35
+ WNS: N/A (combinational)
36
+ Duration: 47.5s
37
+
38
+ --- Multi-Corner STA ---
39
+ Using post-PnR netlist with SPEF back-annotation
40
+ ff_n40C_1v95 (fast) WNS: NaN ns TNS: NaN ns [VIOLATED]
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+ tt_025C_1v80 (typical) WNS: NaN ns TNS: NaN ns [VIOLATED]
42
+ ss_n40C_1v40 (slow) WNS: NaN ns TNS: NaN ns [VIOLATED]
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+
44
+ --- Power Analysis ---
45
+ Power analysis skipped: No Liberty file available (use --liberty or set SKY130_LIBERTY)
46
+
47
+ === Step 3/3: GDS Generation ===
48
+ GDS generation complete: /tmp/datagen_output/mul_w8_unsigned_p0_sky130_500mhz/flow/mul_w8_unsigned_p0.gds
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+
50
+ === Signoff Checks ===
51
+
52
+ --- DRC ---
53
+ DRC: CLEAN
54
+
55
+ --- LVS ---
56
+ LVS: CLEAN
57
+
58
+ ═══════════════════════════════════════════
59
+ RESULTS
60
+ ═══════════════════════════════════════════
61
+
62
+ Synthesis:
63
+ Cells: 244
64
+ Netlist: /tmp/datagen_output/mul_w8_unsigned_p0_sky130_500mhz/flow/netlist.v
65
+
66
+ Place & Route:
67
+ DEF: /tmp/datagen_output/mul_w8_unsigned_p0_sky130_500mhz/flow/output.def
68
+ WNS: N/A (combinational)
69
+ Util: 55.0%
70
+ Instances: 659
71
+ Area: 2220.00 um^2
72
+
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+ GDSII: /tmp/datagen_output/mul_w8_unsigned_p0_sky130_500mhz/flow/mul_w8_unsigned_p0.gds
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+
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+ Multi-Corner STA:
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+ ff_n40C_1v95 (fast) WNS: NaN ns TNS: NaN ns [VIOLATED]
77
+ tt_025C_1v80 (typical) WNS: NaN ns TNS: NaN ns [VIOLATED]
78
+ ss_n40C_1v40 (slow) WNS: NaN ns TNS: NaN ns [VIOLATED]
79
+
80
+ SPEF: /tmp/datagen_output/mul_w8_unsigned_p0_sky130_500mhz/flow/mul_w8_unsigned_p0.spef
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+
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+ Duration: 59.16s
83
+
84
+ Signoff:
85
+ Timing: N/A (combinational)
86
+ DRC: CLEAN
87
+ DRC report: /tmp/datagen_output/mul_w8_unsigned_p0_sky130_500mhz/flow/drc_report.rpt
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+ LVS: CLEAN
89
+ LVS report: /tmp/datagen_output/mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_report.lyrdb
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+
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+ SIGNOFF: PASS
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+
93
+ Flow completed successfully!
94
+
mul_w8_unsigned_p0_sky130_500mhz/flow/klayout_lvs.log ADDED
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+ Elapsed: 0.000s Memory: 590.00M
95
+ "polygons" in: lvs_deck_patched.lylvs:80
96
+ Polygons (raw): 0 (flat) 0 (hierarchical)
97
+ Elapsed: 0.000s Memory: 590.00M
98
+ "polygons" in: lvs_deck_patched.lylvs:81
99
+ Polygons (raw): 0 (flat) 0 (hierarchical)
100
+ Elapsed: 0.000s Memory: 590.00M
101
+ "polygons" in: lvs_deck_patched.lylvs:82
102
+ Polygons (raw): 0 (flat) 0 (hierarchical)
103
+ Elapsed: 0.000s Memory: 590.00M
104
+ "polygons" in: lvs_deck_patched.lylvs:83
105
+ Polygons (raw): 3791 (flat) 395 (hierarchical)
106
+ Elapsed: 0.000s Memory: 591.00M
107
+ "input" in: lvs_deck_patched.lylvs:84
108
+ Polygons (raw): 1157 (flat) 198 (hierarchical)
109
+ Elapsed: 0.000s Memory: 591.00M
110
+ "polygons" in: lvs_deck_patched.lylvs:85
111
+ Polygons (raw): 1359 (flat) 216 (hierarchical)
112
+ Elapsed: 0.000s Memory: 591.00M
113
+ "polygons" in: lvs_deck_patched.lylvs:86
114
+ Polygons (raw): 0 (flat) 0 (hierarchical)
115
+ Elapsed: 0.000s Memory: 591.00M
116
+ "polygons" in: lvs_deck_patched.lylvs:87
117
+ Polygons (raw): 4150 (flat) 463 (hierarchical)
118
+ Elapsed: 0.000s Memory: 591.00M
119
+ "polygons" in: lvs_deck_patched.lylvs:88
120
+ Polygons (raw): 3359 (flat) 1084 (hierarchical)
121
+ Elapsed: 0.000s Memory: 591.00M
122
+ "input" in: lvs_deck_patched.lylvs:89
123
+ Polygons (raw): 588 (flat) 66 (hierarchical)
124
+ Elapsed: 0.000s Memory: 591.00M
125
+ "polygons" in: lvs_deck_patched.lylvs:90
126
+ Polygons (raw): 590 (flat) 68 (hierarchical)
127
+ Elapsed: 0.000s Memory: 591.00M
128
+ "polygons" in: lvs_deck_patched.lylvs:91
129
+ Polygons (raw): 0 (flat) 0 (hierarchical)
130
+ Elapsed: 0.000s Memory: 591.00M
131
+ "polygons" in: lvs_deck_patched.lylvs:92
132
+ Polygons (raw): 1045 (flat) 6 (hierarchical)
133
+ Elapsed: 0.000s Memory: 591.00M
134
+ "polygons" in: lvs_deck_patched.lylvs:93
135
+ Polygons (raw): 1626 (flat) 667 (hierarchical)
136
+ Elapsed: 0.010s Memory: 591.00M
137
+ "input" in: lvs_deck_patched.lylvs:94
138
+ Polygons (raw): 32 (flat) 32 (hierarchical)
139
+ Elapsed: 0.000s Memory: 592.00M
140
+ "polygons" in: lvs_deck_patched.lylvs:95
141
+ Polygons (raw): 32 (flat) 32 (hierarchical)
142
+ Elapsed: 0.000s Memory: 592.00M
143
+ "polygons" in: lvs_deck_patched.lylvs:96
144
+ Polygons (raw): 0 (flat) 0 (hierarchical)
145
+ Elapsed: 0.000s Memory: 592.00M
146
+ "polygons" in: lvs_deck_patched.lylvs:97
147
+ Polygons (raw): 254 (flat) 5 (hierarchical)
148
+ Elapsed: 0.000s Memory: 592.00M
149
+ "polygons" in: lvs_deck_patched.lylvs:98
150
+ Polygons (raw): 251 (flat) 95 (hierarchical)
151
+ Elapsed: 0.000s Memory: 592.00M
152
+ "input" in: lvs_deck_patched.lylvs:99
153
+ Polygons (raw): 0 (flat) 0 (hierarchical)
154
+ Elapsed: 0.000s Memory: 592.00M
155
+ "polygons" in: lvs_deck_patched.lylvs:100
156
+ Polygons (raw): 0 (flat) 0 (hierarchical)
157
+ Elapsed: 0.000s Memory: 592.00M
158
+ "polygons" in: lvs_deck_patched.lylvs:101
159
+ Polygons (raw): 0 (flat) 0 (hierarchical)
160
+ Elapsed: 0.000s Memory: 592.00M
161
+ "polygons" in: lvs_deck_patched.lylvs:102
162
+ Polygons (raw): 194 (flat) 5 (hierarchical)
163
+ Elapsed: 0.010s Memory: 592.00M
164
+ "polygons" in: lvs_deck_patched.lylvs:103
165
+ Polygons (raw): 63 (flat) 8 (hierarchical)
166
+ Elapsed: 0.000s Memory: 592.00M
167
+ "input" in: lvs_deck_patched.lylvs:104
168
+ Polygons (raw): 0 (flat) 0 (hierarchical)
169
+ Elapsed: 0.000s Memory: 593.00M
170
+ "polygons" in: lvs_deck_patched.lylvs:105
171
+ Polygons (raw): 0 (flat) 0 (hierarchical)
172
+ Elapsed: 0.000s Memory: 593.00M
173
+ "polygons" in: lvs_deck_patched.lylvs:106
174
+ Polygons (raw): 0 (flat) 0 (hierarchical)
175
+ Elapsed: 0.000s Memory: 593.00M
176
+ "polygons" in: lvs_deck_patched.lylvs:107
177
+ Polygons (raw): 8 (flat) 1 (hierarchical)
178
+ Elapsed: 0.000s Memory: 593.00M
179
+ "polygons" in: lvs_deck_patched.lylvs:108
180
+ Polygons (raw): 12 (flat) 5 (hierarchical)
181
+ Elapsed: 0.000s Memory: 593.00M
182
+ "input" in: lvs_deck_patched.lylvs:109
183
+ Polygons (raw): 2 (flat) 2 (hierarchical)
184
+ Elapsed: 0.000s Memory: 593.00M
185
+ "polygons" in: lvs_deck_patched.lylvs:110
186
+ Polygons (raw): 4 (flat) 4 (hierarchical)
187
+ Elapsed: 0.000s Memory: 593.00M
188
+ "polygons" in: lvs_deck_patched.lylvs:111
189
+ Polygons (raw): 0 (flat) 0 (hierarchical)
190
+ Elapsed: 0.000s Memory: 593.00M
191
+ "polygons" in: lvs_deck_patched.lylvs:112
192
+ Polygons (raw): 0 (flat) 0 (hierarchical)
193
+ Elapsed: 0.000s Memory: 593.00M
194
+ "input" in: lvs_deck_patched.lylvs:113
195
+ Polygons (raw): 0 (flat) 0 (hierarchical)
196
+ Elapsed: 0.000s Memory: 593.00M
197
+ "polygons" in: lvs_deck_patched.lylvs:114
198
+ Polygons (raw): 0 (flat) 0 (hierarchical)
199
+ Elapsed: 0.000s Memory: 593.00M
200
+ "polygons" in: lvs_deck_patched.lylvs:115
201
+ Polygons (raw): 0 (flat) 0 (hierarchical)
202
+ Elapsed: 0.000s Memory: 593.00M
203
+ "polygons" in: lvs_deck_patched.lylvs:116
204
+ Polygons (raw): 0 (flat) 0 (hierarchical)
205
+ Elapsed: 0.000s Memory: 594.00M
206
+ "polygons" in: lvs_deck_patched.lylvs:117
207
+ Polygons (raw): 0 (flat) 0 (hierarchical)
208
+ Elapsed: 0.000s Memory: 594.00M
209
+ "polygons" in: lvs_deck_patched.lylvs:118
210
+ Polygons (raw): 0 (flat) 0 (hierarchical)
211
+ Elapsed: 0.000s Memory: 594.00M
212
+ "polygons" in: lvs_deck_patched.lylvs:119
213
+ Polygons (raw): 0 (flat) 0 (hierarchical)
214
+ Elapsed: 0.000s Memory: 594.00M
215
+ "polygons" in: lvs_deck_patched.lylvs:120
216
+ Polygons (raw): 0 (flat) 0 (hierarchical)
217
+ Elapsed: 0.000s Memory: 594.00M
218
+ "polygons" in: lvs_deck_patched.lylvs:121
219
+ Polygons (raw): 0 (flat) 0 (hierarchical)
220
+ Elapsed: 0.000s Memory: 594.00M
221
+ "polygons" in: lvs_deck_patched.lylvs:122
222
+ Polygons (raw): 0 (flat) 0 (hierarchical)
223
+ Elapsed: 0.000s Memory: 594.00M
224
+ "polygons" in: lvs_deck_patched.lylvs:123
225
+ Polygons (raw): 0 (flat) 0 (hierarchical)
226
+ Elapsed: 0.000s Memory: 594.00M
227
+ "polygons" in: lvs_deck_patched.lylvs:126
228
+ Polygons (raw): 244 (flat) 32 (hierarchical)
229
+ Elapsed: 0.000s Memory: 594.00M
230
+ "&" in: lvs_deck_patched.lylvs:130
231
+ Polygons (raw): 330 (flat) 45 (hierarchical)
232
+ Elapsed: 0.000s Memory: 1146.00M
233
+ "&" in: lvs_deck_patched.lylvs:130
234
+ Polygons (raw): 330 (flat) 45 (hierarchical)
235
+ Elapsed: 0.020s Memory: 1146.00M
236
+ "&" in: lvs_deck_patched.lylvs:131
237
+ Polygons (raw): 50 (flat) 1 (hierarchical)
238
+ Elapsed: 0.000s Memory: 1146.00M
239
+ "&" in: lvs_deck_patched.lylvs:131
240
+ Polygons (raw): 50 (flat) 1 (hierarchical)
241
+ Elapsed: 0.000s Memory: 1177.00M
242
+ "&" in: lvs_deck_patched.lylvs:132
243
+ Polygons (raw): 1084 (flat) 151 (hierarchical)
244
+ Elapsed: 0.020s Memory: 1137.00M
245
+ "-" in: lvs_deck_patched.lylvs:133
246
+ Polygons (raw): 1414 (flat) 196 (hierarchical)
247
+ Elapsed: 0.000s Memory: 1137.00M
248
+ "-" in: lvs_deck_patched.lylvs:134
249
+ Polygons (raw): 0 (flat) 0 (hierarchical)
250
+ Elapsed: 0.010s Memory: 1167.00M
251
+ "-" in: lvs_deck_patched.lylvs:134
252
+ Polygons (raw): 0 (flat) 0 (hierarchical)
253
+ Elapsed: 0.000s Memory: 1137.00M
254
+ "-" in: lvs_deck_patched.lylvs:134
255
+ Polygons (raw): 0 (flat) 0 (hierarchical)
256
+ Elapsed: 0.000s Memory: 1137.00M
257
+ "-" in: lvs_deck_patched.lylvs:135
258
+ Polygons (raw): 294 (flat) 33 (hierarchical)
259
+ Elapsed: 0.000s Memory: 1137.00M
260
+ "-" in: lvs_deck_patched.lylvs:135
261
+ Polygons (raw): 294 (flat) 33 (hierarchical)
262
+ Elapsed: 0.000s Memory: 1137.00M
263
+ "&" in: lvs_deck_patched.lylvs:135
264
+ Polygons (raw): 1084 (flat) 151 (hierarchical)
265
+ Elapsed: 0.000s Memory: 1157.00M
266
+ "-" in: lvs_deck_patched.lylvs:136
267
+ Polygons (raw): 0 (flat) 0 (hierarchical)
268
+ Elapsed: 0.010s Memory: 1137.00M
269
+ "-" in: lvs_deck_patched.lylvs:136
270
+ Polygons (raw): 0 (flat) 0 (hierarchical)
271
+ Elapsed: 0.000s Memory: 1137.00M
272
+ "&" in: lvs_deck_patched.lylvs:136
273
+ Polygons (raw): 0 (flat) 0 (hierarchical)
274
+ Elapsed: 0.000s Memory: 1137.00M
275
+ "-" in: lvs_deck_patched.lylvs:138
276
+ Polygons (raw): 350 (flat) 48 (hierarchical)
277
+ Elapsed: 0.000s Memory: 1147.00M
278
+ "&" in: lvs_deck_patched.lylvs:138
279
+ Polygons (raw): 350 (flat) 48 (hierarchical)
280
+ Elapsed: 0.000s Memory: 1158.00M
281
+ "-" in: lvs_deck_patched.lylvs:139
282
+ Polygons (raw): 50 (flat) 1 (hierarchical)
283
+ Elapsed: 0.010s Memory: 1168.00M
284
+ "&" in: lvs_deck_patched.lylvs:139
285
+ Polygons (raw): 50 (flat) 1 (hierarchical)
286
+ Elapsed: 0.000s Memory: 1158.00M
287
+ "&" in: lvs_deck_patched.lylvs:140
288
+ Polygons (raw): 1083 (flat) 150 (hierarchical)
289
+ Elapsed: 0.000s Memory: 1148.00M
290
+ "-" in: lvs_deck_patched.lylvs:141
291
+ Polygons (raw): 1433 (flat) 198 (hierarchical)
292
+ Elapsed: 0.010s Memory: 1158.00M
293
+ "-" in: lvs_deck_patched.lylvs:142
294
+ Polygons (raw): 1083 (flat) 150 (hierarchical)
295
+ Elapsed: 0.000s Memory: 1138.00M
296
+ "-" in: lvs_deck_patched.lylvs:142
297
+ Polygons (raw): 1083 (flat) 150 (hierarchical)
298
+ Elapsed: 0.000s Memory: 1138.00M
299
+ "-" in: lvs_deck_patched.lylvs:142
300
+ Polygons (raw): 1083 (flat) 150 (hierarchical)
301
+ Elapsed: 0.000s Memory: 1138.00M
302
+ "-" in: lvs_deck_patched.lylvs:143
303
+ Polygons (raw): 1083 (flat) 150 (hierarchical)
304
+ Elapsed: 0.000s Memory: 1138.00M
305
+ "-" in: lvs_deck_patched.lylvs:143
306
+ Polygons (raw): 0 (flat) 0 (hierarchical)
307
+ Elapsed: 0.000s Memory: 1138.00M
308
+ "&" in: lvs_deck_patched.lylvs:143
309
+ Polygons (raw): 0 (flat) 0 (hierarchical)
310
+ Elapsed: 0.000s Memory: 1138.00M
311
+ "-" in: lvs_deck_patched.lylvs:144
312
+ Polygons (raw): 1083 (flat) 150 (hierarchical)
313
+ Elapsed: 0.000s Memory: 1138.00M
314
+ "-" in: lvs_deck_patched.lylvs:144
315
+ Polygons (raw): 1083 (flat) 150 (hierarchical)
316
+ Elapsed: 0.000s Memory: 1139.00M
317
+ "&" in: lvs_deck_patched.lylvs:144
318
+ Polygons (raw): 0 (flat) 0 (hierarchical)
319
+ Elapsed: 0.000s Memory: 1139.00M
320
+ "-" in: lvs_deck_patched.lylvs:145
321
+ Polygons (raw): 1083 (flat) 150 (hierarchical)
322
+ Elapsed: 0.000s Memory: 1139.00M
323
+ "&" in: lvs_deck_patched.lylvs:145
324
+ Polygons (raw): 0 (flat) 0 (hierarchical)
325
+ Elapsed: 0.000s Memory: 1139.00M
326
+ "&" in: lvs_deck_patched.lylvs:145
327
+ Polygons (raw): 0 (flat) 0 (hierarchical)
328
+ Elapsed: 0.000s Memory: 1139.00M
329
+ "extract_devices" in: lvs_deck_patched.lylvs:151
330
+ Elapsed: 0.010s Memory: 1139.00M
331
+ "extract_devices" in: lvs_deck_patched.lylvs:152
332
+ Elapsed: 0.010s Memory: 1140.00M
333
+ "extract_devices" in: lvs_deck_patched.lylvs:153
334
+ Elapsed: 0.020s Memory: 1140.00M
335
+ "extract_devices" in: lvs_deck_patched.lylvs:156
336
+ Elapsed: 0.010s Memory: 1140.00M
337
+ "extract_devices" in: lvs_deck_patched.lylvs:157
338
+ Elapsed: 0.020s Memory: 1141.00M
339
+ "extract_devices" in: lvs_deck_patched.lylvs:158
340
+ Elapsed: 0.010s Memory: 1141.00M
341
+ "extract_devices" in: lvs_deck_patched.lylvs:159
342
+ Elapsed: 0.010s Memory: 1141.00M
343
+ "netlist" in: lvs_deck_patched.lylvs:199
344
+ Elapsed: 0.110s Memory: 1144.00M
345
+ Flatten layout cell (no schematic): VIA_via4_5_1600_480_1_4_400_400
346
+ Flatten layout cell (no schematic): VIA_via3_4_1600_480_1_4_400_400
347
+ Flatten layout cell (no schematic): VIA_via2_3_1600_480_1_5_320_320
348
+ Flatten layout cell (no schematic): VIA_via5_6_1600_1600_1_1_1600_1600
349
+ Flatten layout cell (no schematic): VIA_L1M1_PR_MR
350
+ Flatten layout cell (no schematic): VIA_M1M2_PR
351
+ Flatten layout cell (no schematic): VIA_M2M3_PR
352
+ Flatten layout cell (no schematic): VIA_L1M1_PR
353
+ Flatten layout cell (no schematic): VIA_M3M4_PR
354
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_0
355
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_1
356
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_2
357
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_4
358
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111O_1
359
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111O_2
360
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111O_4
361
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211OI_2
362
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211OI_4
363
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211O_1
364
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211O_2
365
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211O_4
366
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_0
367
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_1
368
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_2
369
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_4
370
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BO_1
371
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BO_2
372
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BO_4
373
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21OI_2
374
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21OI_4
375
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21O_1
376
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21O_2
377
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21O_4
378
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221OI_1
379
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221OI_2
380
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221OI_4
381
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221O_1
382
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221O_2
383
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221O_4
384
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A222OI_1
385
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22OI_2
386
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22OI_4
387
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22O_2
388
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22O_4
389
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2OI_1
390
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2OI_2
391
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2OI_4
392
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2O_1
393
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2O_2
394
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2O_4
395
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311OI_1
396
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311OI_2
397
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311OI_4
398
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311O_1
399
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311O_2
400
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311O_4
401
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31OI_4
402
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31O_1
403
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31O_2
404
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31O_4
405
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32OI_1
406
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32OI_2
407
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32OI_4
408
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32O_1
409
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32O_2
410
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32O_4
411
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41OI_1
412
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41OI_2
413
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41OI_4
414
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41O_1
415
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41O_2
416
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41O_4
417
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2B_1
418
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2B_2
419
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2B_4
420
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2_1
421
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2_2
422
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2_4
423
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3B_1
424
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3B_2
425
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3B_4
426
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3_1
427
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3_2
428
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3_4
429
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4BB_1
430
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4BB_2
431
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4BB_4
432
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4B_1
433
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4B_2
434
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4B_4
435
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4_1
436
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4_2
437
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4_4
438
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFBUF_16
439
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFBUF_8
440
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFINV_16
441
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFINV_8
442
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_1
443
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_12
444
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_16
445
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_2
446
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_4
447
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_6
448
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_8
449
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_1
450
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_16
451
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_2
452
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_4
453
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_8
454
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S15_1
455
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S15_2
456
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S18_1
457
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S18_2
458
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S25_1
459
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S25_2
460
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S50_1
461
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S50_2
462
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINVLP_2
463
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINVLP_4
464
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_16
465
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_2
466
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_4
467
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_8
468
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_12
469
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_3
470
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_4
471
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_6
472
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_8
473
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFBBN_1
474
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFBBN_2
475
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFBBP_1
476
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRBP_1
477
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRBP_2
478
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTN_1
479
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTP_1
480
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTP_2
481
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTP_4
482
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSBP_1
483
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSBP_2
484
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSTP_1
485
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSTP_2
486
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSTP_4
487
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXBP_1
488
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXBP_2
489
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXTP_1
490
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXTP_2
491
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXTP_4
492
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DIODE_2
493
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLCLKP_1
494
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLCLKP_2
495
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLCLKP_4
496
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBN_1
497
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBN_2
498
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBP_1
499
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBP_2
500
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTN_1
501
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTN_2
502
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTN_4
503
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTP_1
504
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTP_2
505
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTP_4
506
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXBN_1
507
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXBN_2
508
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXBP_1
509
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTN_1
510
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTN_2
511
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTN_4
512
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTP_1
513
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYGATE4SD1_1
514
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYGATE4SD2_1
515
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYGATE4SD3_1
516
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYMETAL6S2S_1
517
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYMETAL6S4S_1
518
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYMETAL6S6S_1
519
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_1
520
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_2
521
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_4
522
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_8
523
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EDFXBP_1
524
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EDFXTP_1
525
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_0
526
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_1
527
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_2
528
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_4
529
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_8
530
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_1
531
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_2
532
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_4
533
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_8
534
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FAHCIN_1
535
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FAHCON_1
536
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FAH_1
537
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FA_1
538
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FA_2
539
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FA_4
540
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_1
541
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_2
542
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_4
543
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_8
544
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__HA_1
545
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__HA_2
546
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__HA_4
547
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_12
548
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_16
549
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_4
550
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_6
551
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_8
552
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_BLEEDER_1
553
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1
554
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16
555
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2
556
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4
557
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8
558
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1
559
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16
560
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2
561
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4
562
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8
563
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12
564
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3
565
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4
566
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6
567
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8
568
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1
569
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1
570
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1
571
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1
572
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16
573
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16
574
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2
575
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4
576
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8
577
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1
578
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2
579
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4
580
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4
581
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1
582
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2
583
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4
584
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MACRO_SPARECELL
585
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CONB_1
586
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2_2
587
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2_2
588
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_2
589
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MAJ3_2
590
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MAJ3_4
591
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2I_1
592
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2I_2
593
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2I_4
594
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_1
595
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_2
596
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_4
597
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_8
598
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX4_1
599
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX4_2
600
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX4_4
601
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2B_2
602
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2B_4
603
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2_4
604
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2_8
605
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3B_1
606
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3B_2
607
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3B_4
608
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3_2
609
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3_4
610
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4BB_1
611
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4BB_2
612
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4BB_4
613
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4B_1
614
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4B_2
615
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4B_4
616
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4_1
617
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4_4
618
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2B_2
619
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2B_4
620
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2_4
621
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2_8
622
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3B_2
623
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3B_4
624
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3_2
625
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3_4
626
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4BB_1
627
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4BB_2
628
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4BB_4
629
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4B_1
630
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4B_2
631
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4B_4
632
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4_1
633
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4_2
634
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4_4
635
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111AI_1
636
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111AI_2
637
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111AI_4
638
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111A_1
639
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111A_2
640
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111A_4
641
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211AI_4
642
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211A_1
643
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211A_2
644
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211A_4
645
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21AI_4
646
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21A_2
647
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21A_4
648
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BAI_1
649
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BAI_2
650
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BAI_4
651
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BA_1
652
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BA_2
653
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BA_4
654
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221AI_1
655
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221AI_2
656
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221AI_4
657
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221A_1
658
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221A_2
659
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221A_4
660
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22AI_1
661
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22AI_2
662
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22AI_4
663
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22A_1
664
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22A_2
665
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22A_4
666
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2AI_1
667
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2AI_2
668
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2AI_4
669
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2A_1
670
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2A_2
671
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2A_4
672
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311AI_0
673
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311AI_1
674
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311AI_2
675
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311AI_4
676
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311A_1
677
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311A_2
678
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311A_4
679
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31AI_1
680
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31AI_2
681
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31AI_4
682
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31A_1
683
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31A_2
684
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31A_4
685
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32AI_1
686
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32AI_2
687
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32AI_4
688
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32A_1
689
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32A_2
690
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32A_4
691
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41AI_1
692
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41AI_2
693
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41AI_4
694
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41A_1
695
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41A_2
696
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41A_4
697
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2B_1
698
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2B_2
699
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2B_4
700
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_0
701
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_1
702
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_2
703
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_4
704
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3B_1
705
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3B_2
706
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3B_4
707
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3_2
708
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3_4
709
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4BB_1
710
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4BB_2
711
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4BB_4
712
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4B_1
713
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4B_2
714
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4B_4
715
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4_1
716
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4_2
717
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4_4
718
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__PROBEC_P_8
719
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__PROBE_P_8
720
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFBBN_1
721
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFBBN_2
722
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFBBP_1
723
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRBP_1
724
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRBP_2
725
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTN_1
726
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTP_1
727
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTP_2
728
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTP_4
729
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSBP_1
730
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSBP_2
731
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSTP_1
732
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSTP_2
733
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSTP_4
734
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXBP_1
735
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXBP_2
736
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXTP_1
737
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXTP_2
738
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXTP_4
739
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDLCLKP_1
740
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDLCLKP_2
741
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDLCLKP_4
742
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXBP_1
743
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXBP_2
744
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXTP_1
745
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXTP_2
746
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXTP_4
747
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAPVGND2_1
748
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAPVGND_1
749
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAP_1
750
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAP_2
751
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR2_2
752
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR2_4
753
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR3_4
754
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR2_2
755
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR2_4
756
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR3_2
757
+ Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR3_4
758
+ Writing netlist: /tmp/datagen_output/mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_extracted.cir ..
759
+ Writing LVS database: /tmp/datagen_output/mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_report.lyrdb ..
760
+ Total elapsed: 0.760s Memory: 1152.00M
761
+ INFO : Congratulations! Netlists match.
762
+
763
+ === stderr ===
mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_cleaned.gds.gz ADDED
@@ -0,0 +1,3 @@
 
 
 
 
1
+ version https://git-lfs.github.com/spec/v1
2
+ oid sha256:5453c78cdd395f5d12564b2d710441ad3bc88bcecfd9568673178e84f82106b2
3
+ size 60751
mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_deck_patched.lylvs ADDED
@@ -0,0 +1,295 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ <?xml version="1.0" encoding="utf-8"?>
2
+ <klayout-macro>
3
+ <description/>
4
+ <version/>
5
+ <category>lvs</category>
6
+ <prolog/>
7
+ <epilog/>
8
+ <doc/>
9
+ <autorun>false</autorun>
10
+ <autorun-early>false</autorun-early>
11
+ <shortcut/>
12
+ <show-in-menu>true</show-in-menu>
13
+ <group-name>lvs_scripts</group-name>
14
+ <menu-path>tools_menu.lvs.end</menu-path>
15
+ <interpreter>dsl</interpreter>
16
+ <dsl-interpreter-name>lvs-dsl-xml</dsl-interpreter-name>
17
+ <text>#
18
+ # Extraction for SKY130
19
+ #
20
+ ############################
21
+
22
+ # optionnal for a batch launch : klayout -b -rd in_gds=my_layout.gds -rd report_file=my_report.lyrdb -rd cdl_file=reference_netlist.cir -rd target_netlist=extracted_netlist.cir -r sky130.lylvs
23
+ if $in_gds
24
+ source($in_gds)
25
+ end
26
+
27
+ if $report_file
28
+ report_lvs($report_file)
29
+ else
30
+ report_lvs("lvs_report.lvsdb")
31
+ end
32
+
33
+ if $cdl_file
34
+ #reference netlist
35
+ schematic($cdl_file)
36
+ else
37
+ schematic("sky130hd.cdl")
38
+ end
39
+
40
+ # true: use net names instead of numbers
41
+ # false: use numbers for nets
42
+ spice_with_net_names = true
43
+
44
+ # true: put in comments with details
45
+ # false: no comments
46
+ spice_with_comments = false
47
+
48
+ if $target_netlist
49
+ target_netlist($target_netlist)
50
+ else
51
+ # target_netlist("netlist.cir", write_spice(spice_with_net_names, spice_with_comments), "The netlist comment goes here.")
52
+ target_netlist(File.join(File.dirname(RBA::CellView::active.filename), source.cell_name+"_extracted.cir"), write_spice(spice_with_net_names, spice_with_comments), "Extracted by KLayout on : #{Time.now.strftime("%d/%m/%Y %H:%M")}")
53
+ end
54
+
55
+ # Hierarchical mode
56
+ deep
57
+ # Use 4 CPU cores
58
+ threads(4)
59
+ # Print details
60
+ verbose(true)
61
+
62
+
63
+ # layers definitions
64
+ ########################
65
+ BOUND = polygons(235, 4)
66
+ DNWELL = polygons(64, 18)
67
+ PWRES = polygons(64, 13)
68
+ NWELL = polygons(64, 20)
69
+ NWELLTXT = input(64, 5)
70
+ NWELLPIN = polygons(64, 16)
71
+ SUBTXT = input(122, 5)
72
+ SUBPIN = input(64, 59)
73
+ DIFF = polygons(65, 20)
74
+ TAP = polygons(65, 44)
75
+ PSDM = polygons(94, 20)
76
+ NSDM = polygons(93, 44)
77
+ LVTN = polygons(125, 44)
78
+ HVTR = polygons(18, 20)
79
+ HVTP = polygons(78, 44)
80
+ SONOS = polygons(80, 20)
81
+ COREID = polygons(81, 2)
82
+ STDCELL = polygons(81, 4)
83
+ NPNID = polygons(82, 20)
84
+ PNPID = polygons(82, 44)
85
+ RPM = polygons(86, 20)
86
+ URPM = polygons(79, 20)
87
+ LDNTM = polygons(11, 44)
88
+ HVNTM = polygons(125, 20)
89
+ POLY = polygons(66, 20)
90
+ POLYTXT = input(66, 5)
91
+ POLYPIN = polygons(66, 16)
92
+ HVI = polygons(75, 20)
93
+ LICON = polygons(66, 44)
94
+ NPC = polygons(95, 20)
95
+ DIFFRES = polygons(65, 13)
96
+ POLYRES = polygons(66, 13)
97
+ POLYSHO = polygons(66, 15)
98
+ DIODE = polygons(81, 23)
99
+ LI = polygons(67, 20)
100
+ LITXT = input(67, 5)
101
+ LIPIN = polygons(67, 16)
102
+ LIRES = polygons(67, 13)
103
+ MCON = polygons(67, 44)
104
+ MET1 = polygons(68, 20)
105
+ MET1TXT = input(68, 5)
106
+ MET1PIN = polygons(68, 16)
107
+ MET1RES = polygons(68, 13)
108
+ VIA1 = polygons(68, 44)
109
+ MET2 = polygons(69, 20)
110
+ MET2TXT = input(69, 5)
111
+ MET2PIN = polygons(69, 16)
112
+ MET2RES = polygons(69, 13)
113
+ VIA2 = polygons(69, 44)
114
+ MET3 = polygons(70, 20)
115
+ MET3TXT = input(70, 5)
116
+ MET3PIN = polygons(70, 16)
117
+ MET3RES = polygons(70, 13)
118
+ VIA3 = polygons(70, 44)
119
+ MET4 = polygons(71, 20)
120
+ MET4TXT = input(71, 5)
121
+ MET4PIN = polygons(71, 16)
122
+ MET4RES = polygons(71, 13)
123
+ VIA4 = polygons(71, 44)
124
+ MET5 = polygons(72, 20)
125
+ MET5TXT = input(72, 5)
126
+ MET5PIN = polygons(72, 16)
127
+ MET5RES = polygons(72, 13)
128
+ RDL = polygons(74, 20)
129
+ RDLTXT = input(74, 5)
130
+ RDLPIN = polygons(74, 16)
131
+ GLASS = polygons(76, 20)
132
+ CAPM = polygons(89, 44)
133
+ CAPM2 = polygons(97, 44)
134
+ LOWTAPD = polygons(81, 14)
135
+ FILLOBSM1 = polygons(62, 24)
136
+ FILLOBSM2 = polygons(105, 52)
137
+ FILLOBSM3 = polygons(107, 24)
138
+ FILLOBSM4 = polygons(112, 4)
139
+ NCM = polygons(92, 44)
140
+
141
+ # Bulk layer for terminal provisioning
142
+ SUB = polygons(236, 0)
143
+ # SUB = polygon_layer
144
+
145
+ # Computed layers
146
+ PDIFF = DIFF &amp; NWELL &amp; PSDM
147
+ NTAP = TAP &amp; NWELL &amp; NSDM
148
+ PGATE = PDIFF &amp; POLY
149
+ PSD = PDIFF - PGATE
150
+ STD_PGATE = PGATE - HVTP - NCM - HVI
151
+ HVT_PGATE = PGATE &amp; HVTP - NCM - HVI
152
+ HV5_PGATE = PGATE - HVTP - NCM &amp; HVI
153
+
154
+ NDIFF = DIFF - NWELL &amp; NSDM
155
+ PTAP = TAP - NWELL &amp; PSDM
156
+ NGATE = NDIFF &amp; POLY
157
+ NSD = NDIFF - NGATE
158
+ STD_NGATE = NGATE - NCM - LVTN - HVI
159
+ LVT_NGATE = NGATE - NCM &amp; LVTN - HVI
160
+ HV5_NGATE = NGATE - NCM - LVTN &amp; HVI
161
+ HV5NA_NGATE = NGATE - NCM &amp; LVTN &amp; HVI
162
+
163
+ # drawing to physical
164
+ device_scaling(1000000)
165
+
166
+ # PMOS transistor device extraction
167
+ extract_devices(mos4("pfet_01v8"), { "SD" =&gt; PSD, "G" =&gt; STD_PGATE, "tS" =&gt; PSD, "tD" =&gt; PSD, "tG" =&gt; POLY, "W" =&gt; NWELL })
168
+ extract_devices(mos4("pfet_01v8_hvt"), { "SD" =&gt; PSD, "G" =&gt; HVT_PGATE, "tS" =&gt; PSD, "tD" =&gt; PSD, "tG" =&gt; POLY, "W" =&gt; NWELL })
169
+ extract_devices(mos4("pfet_g5v0d10v5"), { "SD" =&gt; PSD, "G" =&gt; HV5_PGATE, "tS" =&gt; PSD, "tD" =&gt; PSD, "tG" =&gt; POLY, "W" =&gt; NWELL })
170
+
171
+ # NMOS transistor device extraction
172
+ extract_devices(mos4("nfet_01v8"), { "SD" =&gt; NSD, "G" =&gt; STD_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
173
+ extract_devices(mos4("nfet_01v8_lvt"), { "SD" =&gt; NSD, "G" =&gt; LVT_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
174
+ extract_devices(mos4("nfet_g5v0d10v5"), { "SD" =&gt; NSD, "G" =&gt; HV5_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
175
+ extract_devices(mos4("nfet_01v8_nvt"), { "SD" =&gt; NSD, "G" =&gt; HV5NA_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
176
+
177
+
178
+ # Define connectivity for netlist extraction
179
+
180
+ # Inter-layer
181
+ connect(SUB, PTAP)
182
+ connect(NWELL, NTAP)
183
+ connect(LICON, PTAP)
184
+ connect(LICON, NTAP)
185
+ connect(PSD, LICON)
186
+ connect(NSD, LICON)
187
+ connect(POLY, LICON)
188
+ connect(LICON, LI)
189
+ connect(LI, MCON)
190
+ connect(MCON, MET1)
191
+ connect(MET1,VIA1)
192
+ connect(VIA1, MET2)
193
+ connect(MET2, VIA2)
194
+ connect(VIA2, MET3)
195
+ connect(MET3, VIA3)
196
+ connect(VIA3, MET4)
197
+ connect(MET4, VIA4)
198
+ connect(VIA4, MET5)
199
+ # Attaching labels
200
+ connect(SUB, SUBTXT)
201
+ connect(SUB, SUBPIN)
202
+ connect(NWELL, NWELLTXT)
203
+ connect(POLY, POLYTXT)
204
+ connect(LI, LITXT)
205
+ connect(MET1, MET1TXT)
206
+ connect(MET2, MET2TXT)
207
+ connect(MET3, MET3TXT)
208
+ connect(MET4, MET4TXT)
209
+ connect(MET5, MET5TXT)
210
+
211
+ # Global
212
+ connect_global(SUB, "VNB")
213
+
214
+ # Actually performs the extraction
215
+ netlist # ... not really required
216
+
217
+ # Flatten cells which are present in one netlist only
218
+ align
219
+
220
+ # Flat LVS: flatten all cells to transistor level.
221
+ # This avoids hierarchical port identification issues where
222
+ # KLayout misses output pins on cells whose LI shapes are
223
+ # only on the PIN datatype (67/16) not DRAWING (67/20).
224
+ netlist.flatten_circuit("*")
225
+ schematic.flatten_circuit("*")
226
+
227
+ netlist.make_top_level_pins
228
+ netlist.combine_devices
229
+ netlist.purge
230
+ schematic.combine_devices
231
+ schematic.purge
232
+
233
+ # Tolerances for the devices extracted parameters
234
+ # tolerance(device_class_name, parameter_name [, :absolute =&gt; absolute_tolerance] [, :relative =&gt; relative_tolerance])
235
+ tolerance("pfet_01v8", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
236
+ tolerance("pfet_01v8", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
237
+ tolerance("pfet_01v8_hvt", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
238
+ tolerance("pfet_01v8_hvt", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
239
+ tolerance("nfet_01v8", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
240
+ tolerance("nfet_01v8", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
241
+ tolerance("nfet_01v8_lvt", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
242
+ tolerance("nfet_01v8_lvt", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
243
+
244
+ # NangateOpenCellLibrary Digital gates input equivalence :
245
+ equivalent_pins("*AND2_1", "A", "B")
246
+ equivalent_pins("*AND2_2", "A", "B")
247
+ equivalent_pins("*AND2_4", "A", "B")
248
+ equivalent_pins("*AND3_1", "A", "B", "C")
249
+ equivalent_pins("*AND3_2", "A", "B", "C")
250
+ equivalent_pins("*AND3_4", "A", "B", "C")
251
+ equivalent_pins("*AND4_1", "A", "B", "C", "D")
252
+ equivalent_pins("*AND4_2", "A", "B", "C", "D")
253
+ equivalent_pins("*AND4_4", "A", "B", "C", "D")
254
+ equivalent_pins("*NAND2_1", "A", "B")
255
+ equivalent_pins("*NAND2_2", "A", "B")
256
+ equivalent_pins("*NAND2_4", "A", "B")
257
+ equivalent_pins("*NAND3_1", "A", "B", "C")
258
+ equivalent_pins("*NAND3_2", "A", "B", "C")
259
+ equivalent_pins("*NAND3_4", "A", "B", "C")
260
+ equivalent_pins("*NAND4_X1", "A", "B", "C", "D")
261
+ equivalent_pins("*NAND4_2", "A", "B", "C", "D")
262
+ equivalent_pins("*NAND4_4", "A", "B", "C", "D")
263
+ equivalent_pins("*OR2_1", "A", "B")
264
+ equivalent_pins("*OR2_2", "A", "B")
265
+ equivalent_pins("*OR2_4", "A", "B")
266
+ equivalent_pins("*OR3_1", "A", "B", "C")
267
+ equivalent_pins("*OR3_2", "A", "B", "C")
268
+ equivalent_pins("*OR3_4", "A", "B", "C")
269
+ equivalent_pins("*OR4_1", "A", "B", "C", "D")
270
+ equivalent_pins("*OR4_2", "A", "B", "C", "D")
271
+ equivalent_pins("*OR4_4", "A", "B", "C", "D")
272
+ equivalent_pins("*NOR2_1", "A", "B")
273
+ equivalent_pins("*NOR2_2", "A", "B")
274
+ equivalent_pins("*NOR2_4", "A", "B")
275
+ equivalent_pins("*NOR3_1", "A", "B", "C")
276
+ equivalent_pins("*NOR3_2", "A", "B", "C")
277
+ equivalent_pins("*NOR3_4", "A", "B", "C")
278
+ equivalent_pins("*NOR4_1", "A", "B", "C", "D")
279
+ equivalent_pins("*NOR4_2", "A", "B", "C", "D")
280
+ equivalent_pins("*NOR4_4", "A", "B", "C", "D")
281
+ equivalent_pins("*XOR2_1", "A", "B")
282
+ equivalent_pins("*XOR2_2", "A", "B")
283
+ equivalent_pins("*XNOR2_1", "A", "B")
284
+ equivalent_pins("*XNOR2_2", "A", "B")
285
+
286
+ #max_res(1000000)
287
+ #min_caps(1e-15)
288
+
289
+ if ! compare
290
+ #raise "ERROR : Netlists don't match"
291
+ puts "ERROR : Netlists don't match"
292
+ else
293
+ puts "INFO : Congratulations! Netlists match."
294
+ end</text>
295
+ </klayout-macro>
mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_extracted.cir ADDED
File without changes
mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_reference.cdl.gz ADDED
@@ -0,0 +1,3 @@
 
 
 
 
1
+ version https://git-lfs.github.com/spec/v1
2
+ oid sha256:929d5d3a0eb52c54f9348d1234be1d98f19e5155de165d599462e5ea425c0e18
3
+ size 27295
mul_w8_unsigned_p0_sky130_500mhz/flow/lvs_report.lyrdb ADDED
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385
+ )
386
+ T(D
387
+ R(l2 (75 -500) (210 1000))
388
+ )
389
+ T(B
390
+ R(l3 (-75 -500) (150 1000))
391
+ )
392
+ )
393
+ D(D$pfet_01v8_hvt$23 pfet_01v8_hvt
394
+ T(S
395
+ R(l2 (-285 -500) (210 1000))
396
+ )
397
+ T(G
398
+ R(l4 (-75 -500) (150 1000))
399
+ )
400
+ T(D
401
+ R(l2 (75 -500) (330 1000))
402
+ )
403
+ T(B
404
+ R(l3 (-75 -500) (150 1000))
405
+ )
406
+ )
407
+ D(D$pfet_01v8_hvt$24 pfet_01v8_hvt
408
+ T(S
409
+ R(l2 (-405 -500) (330 1000))
410
+ )
411
+ T(G
412
+ R(l4 (-75 -500) (150 1000))
413
+ )
414
+ T(D
415
+ R(l2 (75 -500) (360 1000))
416
+ )
417
+ T(B
418
+ R(l3 (-75 -500) (150 1000))
419
+ )
420
+ )
421
+ D(D$pfet_01v8_hvt$25 pfet_01v8_hvt
422
+ T(S
423
+ Q(l2 (-525 -320) (0 1000) (375 0) (0 -360) (75 0) (0 -640))
424
+ )
425
+ T(G
426
+ R(l4 (-75 -320) (150 640))
427
+ )
428
+ T(D
429
+ R(l2 (75 -320) (280 640))
430
+ )
431
+ T(B
432
+ R(l3 (-75 -320) (150 640))
433
+ )
434
+ )
435
+ D(D$pfet_01v8_hvt$26 pfet_01v8_hvt
436
+ T(S
437
+ R(l2 (-355 -500) (280 1000))
438
+ )
439
+ T(G
440
+ R(l4 (-75 -500) (150 1000))
441
+ )
442
+ T(D
443
+ Q(l2 (75 -500) (0 1000) (375 0) (0 -360) (75 0) (0 -640))
444
+ )
445
+ T(B
446
+ R(l3 (-75 -500) (150 1000))
447
+ )
448
+ )
449
+ D(D$pfet_01v8_hvt$27 pfet_01v8_hvt
450
+ T(S
451
+ R(l2 (-395 -420) (320 840))
452
+ )
453
+ T(G
454
+ R(l4 (-75 -420) (150 840))
455
+ )
456
+ T(D
457
+ R(l2 (75 -420) (380 840))
458
+ )
459
+ T(B
460
+ R(l3 (-75 -420) (150 840))
461
+ )
462
+ )
463
+ D(D$pfet_01v8_hvt$28 pfet_01v8_hvt
464
+ T(S
465
+ R(l2 (-455 -420) (380 840))
466
+ )
467
+ T(G
468
+ R(l4 (-75 -420) (150 840))
469
+ )
470
+ T(D
471
+ R(l2 (75 -420) (525 840))
472
+ )
473
+ T(B
474
+ R(l3 (-75 -420) (150 840))
475
+ )
476
+ )
477
+ D(D$pfet_01v8_hvt$29 pfet_01v8_hvt
478
+ T(S
479
+ R(l2 (-335 -500) (260 1000))
480
+ )
481
+ T(G
482
+ R(l4 (-75 -500) (150 1000))
483
+ )
484
+ T(D
485
+ Q(l2 (75 -500) (0 1000) (250 0) (0 -740) (10 0) (0 -260))
486
+ )
487
+ T(B
488
+ R(l3 (-75 -500) (150 1000))
489
+ )
490
+ )
491
+ D(D$pfet_01v8_hvt$30 pfet_01v8_hvt
492
+ T(S
493
+ Q(l2 (-685 -320) (0 840) (500 0) (0 -200) (110 0) (0 -640))
494
+ )
495
+ T(G
496
+ R(l4 (-75 -320) (150 640))
497
+ )
498
+ T(D
499
+ Q(l2 (75 -320) (0 640) (300 0) (0 160) (425 0) (0 -640) (-250 0) (0 -160))
500
+ )
501
+ T(B
502
+ R(l3 (-75 -320) (150 640))
503
+ )
504
+ )
505
+ D(D$pfet_01v8_hvt$31 pfet_01v8_hvt
506
+ T(S
507
+ Q(l2 (-490 -420) (0 340) (-10 0) (0 500) (425 0) (0 -840))
508
+ )
509
+ T(G
510
+ R(l4 (-75 -420) (150 840))
511
+ )
512
+ T(D
513
+ Q(l2 (75 -420) (0 840) (500 0) (0 -200) (110 0) (0 -640))
514
+ )
515
+ T(B
516
+ R(l3 (-75 -420) (150 840))
517
+ )
518
+ )
519
+ D(D$pfet_01v8_hvt$32 pfet_01v8_hvt
520
+ T(S
521
+ R(l2 (-335 -420) (260 840))
522
+ )
523
+ T(G
524
+ R(l4 (-75 -420) (150 840))
525
+ )
526
+ T(D
527
+ R(l2 (75 -420) (270 840))
528
+ )
529
+ T(B
530
+ R(l3 (-75 -420) (150 840))
531
+ )
532
+ )
533
+ D(D$pfet_01v8_hvt$33 pfet_01v8_hvt
534
+ T(S
535
+ R(l2 (-345 -420) (270 840))
536
+ )
537
+ T(G
538
+ R(l4 (-75 -420) (150 840))
539
+ )
540
+ T(D
541
+ R(l2 (75 -420) (280 840))
542
+ )
543
+ T(B
544
+ R(l3 (-75 -420) (150 840))
545
+ )
546
+ )
547
+ D(D$pfet_01v8_hvt$34 pfet_01v8_hvt
548
+ T(S
549
+ R(l2 (-340 -500) (265 1000))
550
+ )
551
+ T(G
552
+ R(l4 (-75 -500) (150 1000))
553
+ )
554
+ T(D
555
+ R(l2 (75 -500) (280 1000))
556
+ )
557
+ T(B
558
+ R(l3 (-75 -500) (150 1000))
559
+ )
560
+ )
561
+ D(D$pfet_01v8_hvt$35 pfet_01v8_hvt
562
+ T(S
563
+ R(l2 (-355 -500) (280 1000))
564
+ )
565
+ T(G
566
+ R(l4 (-75 -500) (150 1000))
567
+ )
568
+ T(D
569
+ R(l2 (75 -500) (295 1000))
570
+ )
571
+ T(B
572
+ R(l3 (-75 -500) (150 1000))
573
+ )
574
+ )
575
+ D(D$pfet_01v8_hvt$36 pfet_01v8_hvt
576
+ T(S
577
+ R(l2 (-370 -500) (295 1000))
578
+ )
579
+ T(G
580
+ R(l4 (-75 -500) (150 1000))
581
+ )
582
+ T(D
583
+ R(l2 (75 -500) (265 1000))
584
+ )
585
+ T(B
586
+ R(l3 (-75 -500) (150 1000))
587
+ )
588
+ )
589
+ D(D$pfet_01v8_hvt$37 pfet_01v8_hvt
590
+ T(S
591
+ R(l2 (-355 -500) (280 1000))
592
+ )
593
+ T(G
594
+ R(l4 (-75 -500) (150 1000))
595
+ )
596
+ T(D
597
+ R(l2 (75 -500) (280 1000))
598
+ )
599
+ T(B
600
+ R(l3 (-75 -500) (150 1000))
601
+ )
602
+ )
603
+ D(D$pfet_01v8_hvt$38 pfet_01v8_hvt
604
+ T(S
605
+ R(l2 (-355 -500) (280 1000))
606
+ )
607
+ T(G
608
+ R(l4 (-75 -500) (150 1000))
609
+ )
610
+ T(D
611
+ R(l2 (75 -500) (310 1000))
612
+ )
613
+ T(B
614
+ R(l3 (-75 -500) (150 1000))
615
+ )
616
+ )
617
+ D(D$pfet_01v8_hvt$39 pfet_01v8_hvt
618
+ T(S
619
+ R(l2 (-385 -500) (310 1000))
620
+ )
621
+ T(G
622
+ R(l4 (-75 -500) (150 1000))
623
+ )
624
+ T(D
625
+ R(l2 (75 -500) (265 1000))
626
+ )
627
+ T(B
628
+ R(l3 (-75 -500) (150 1000))
629
+ )
630
+ )
631
+ D(D$pfet_01v8_hvt$40 pfet_01v8_hvt
632
+ T(S
633
+ R(l2 (-335 -210) (260 420))
634
+ )
635
+ T(G
636
+ R(l4 (-75 -210) (150 420))
637
+ )
638
+ T(D
639
+ Q(l2 (75 -210) (0 420) (130 0) (0 580) (260 0) (0 -1000))
640
+ )
641
+ T(B
642
+ R(l3 (-75 -210) (150 420))
643
+ )
644
+ )
645
+ D(D$pfet_01v8_hvt$41 pfet_01v8_hvt
646
+ T(S
647
+ Q(l2 (-465 -500) (0 420) (130 0) (0 580) (260 0) (0 -1000))
648
+ )
649
+ T(G
650
+ R(l4 (-75 -500) (150 1000))
651
+ )
652
+ T(D
653
+ R(l2 (75 -500) (210 1000))
654
+ )
655
+ T(B
656
+ R(l3 (-75 -500) (150 1000))
657
+ )
658
+ )
659
+ D(D$pfet_01v8_hvt$42 pfet_01v8_hvt
660
+ T(S
661
+ R(l2 (-285 -500) (210 1000))
662
+ )
663
+ T(G
664
+ R(l4 (-75 -500) (150 1000))
665
+ )
666
+ T(D
667
+ R(l2 (75 -500) (260 1000))
668
+ )
669
+ T(B
670
+ R(l3 (-75 -500) (150 1000))
671
+ )
672
+ )
673
+ D(D$pfet_01v8_hvt$43 pfet_01v8_hvt
674
+ T(S
675
+ R(l2 (-355 -500) (280 1000))
676
+ )
677
+ T(G
678
+ R(l4 (-75 -500) (150 1000))
679
+ )
680
+ T(D
681
+ R(l2 (75 -500) (655 1000))
682
+ )
683
+ T(B
684
+ R(l3 (-75 -500) (150 1000))
685
+ )
686
+ )
687
+ D(D$pfet_01v8_hvt$44 pfet_01v8_hvt
688
+ T(S
689
+ R(l2 (-730 -500) (655 1000))
690
+ )
691
+ T(G
692
+ R(l4 (-75 -500) (150 1000))
693
+ )
694
+ T(D
695
+ R(l2 (75 -500) (390 1000))
696
+ )
697
+ T(B
698
+ R(l3 (-75 -500) (150 1000))
699
+ )
700
+ )
701
+ D(D$pfet_01v8_hvt$45 pfet_01v8_hvt
702
+ T(S
703
+ R(l2 (-465 -500) (390 1000))
704
+ )
705
+ T(G
706
+ R(l4 (-75 -500) (150 1000))
707
+ )
708
+ T(D
709
+ R(l2 (75 -500) (305 1000))
710
+ )
711
+ T(B
712
+ R(l3 (-75 -500) (150 1000))
713
+ )
714
+ )
715
+ D(D$pfet_01v8_hvt$46 pfet_01v8_hvt
716
+ T(S
717
+ R(l2 (-380 -500) (305 1000))
718
+ )
719
+ T(G
720
+ R(l4 (-75 -500) (150 1000))
721
+ )
722
+ T(D
723
+ R(l2 (75 -500) (260 1000))
724
+ )
725
+ T(B
726
+ R(l3 (-75 -500) (150 1000))
727
+ )
728
+ )
729
+ D(D$pfet_01v8_hvt$47 pfet_01v8_hvt
730
+ T(S
731
+ R(l2 (-335 -210) (260 420))
732
+ )
733
+ T(G
734
+ R(l4 (-75 -210) (150 420))
735
+ )
736
+ T(D
737
+ Q(l2 (75 -210) (0 420) (75 0) (0 580) (260 0) (0 -1000))
738
+ )
739
+ T(B
740
+ R(l3 (-75 -210) (150 420))
741
+ )
742
+ )
743
+ D(D$pfet_01v8_hvt$48 pfet_01v8_hvt
744
+ T(S
745
+ Q(l2 (-410 -500) (0 420) (75 0) (0 580) (260 0) (0 -1000))
746
+ )
747
+ T(G
748
+ R(l4 (-75 -500) (150 1000))
749
+ )
750
+ T(D
751
+ R(l2 (75 -500) (270 1000))
752
+ )
753
+ T(B
754
+ R(l3 (-75 -500) (150 1000))
755
+ )
756
+ )
757
+ D(D$pfet_01v8_hvt$49 pfet_01v8_hvt
758
+ T(S
759
+ R(l2 (-345 -500) (270 1000))
760
+ )
761
+ T(G
762
+ R(l4 (-75 -500) (150 1000))
763
+ )
764
+ T(D
765
+ R(l2 (75 -500) (265 1000))
766
+ )
767
+ T(B
768
+ R(l3 (-75 -500) (150 1000))
769
+ )
770
+ )
771
+ D(D$pfet_01v8_hvt$50 pfet_01v8_hvt
772
+ T(S
773
+ R(l2 (-335 -500) (260 1000))
774
+ )
775
+ T(G
776
+ R(l4 (-75 -500) (150 1000))
777
+ )
778
+ T(D
779
+ R(l2 (75 -500) (210 1000))
780
+ )
781
+ T(B
782
+ R(l3 (-75 -500) (150 1000))
783
+ )
784
+ )
785
+ D(D$pfet_01v8_hvt$51 pfet_01v8_hvt
786
+ T(S
787
+ R(l2 (-395 -500) (320 1000))
788
+ )
789
+ T(G
790
+ R(l4 (-75 -500) (150 1000))
791
+ )
792
+ T(D
793
+ R(l2 (75 -500) (270 1000))
794
+ )
795
+ T(B
796
+ R(l3 (-75 -500) (150 1000))
797
+ )
798
+ )
799
+ D(D$pfet_01v8_hvt$52 pfet_01v8_hvt
800
+ T(S
801
+ R(l2 (-345 -500) (270 1000))
802
+ )
803
+ T(G
804
+ R(l4 (-75 -500) (150 1000))
805
+ )
806
+ T(D
807
+ Q(l2 (75 -500) (0 1000) (290 0) (0 -360) (75 0) (0 -640))
808
+ )
809
+ T(B
810
+ R(l3 (-75 -500) (150 1000))
811
+ )
812
+ )
813
+ D(D$pfet_01v8_hvt$53 pfet_01v8_hvt
814
+ T(S
815
+ R(l2 (-355 -500) (280 1000))
816
+ )
817
+ T(G
818
+ R(l4 (-75 -500) (150 1000))
819
+ )
820
+ T(D
821
+ R(l2 (75 -500) (350 1000))
822
+ )
823
+ T(B
824
+ R(l3 (-75 -500) (150 1000))
825
+ )
826
+ )
827
+ D(D$pfet_01v8_hvt$54 pfet_01v8_hvt
828
+ T(S
829
+ R(l2 (-425 -500) (350 1000))
830
+ )
831
+ T(G
832
+ R(l4 (-75 -500) (150 1000))
833
+ )
834
+ T(D
835
+ R(l2 (75 -500) (320 1000))
836
+ )
837
+ T(B
838
+ R(l3 (-75 -500) (150 1000))
839
+ )
840
+ )
841
+ D(D$pfet_01v8_hvt$55 pfet_01v8_hvt
842
+ T(S
843
+ R(l2 (-395 -500) (320 1000))
844
+ )
845
+ T(G
846
+ R(l4 (-75 -500) (150 1000))
847
+ )
848
+ T(D
849
+ R(l2 (75 -500) (280 1000))
850
+ )
851
+ T(B
852
+ R(l3 (-75 -500) (150 1000))
853
+ )
854
+ )
855
+ D(D$pfet_01v8_hvt$56 pfet_01v8_hvt
856
+ T(S
857
+ R(l2 (-355 -500) (280 1000))
858
+ )
859
+ T(G
860
+ R(l4 (-75 -500) (150 1000))
861
+ )
862
+ T(D
863
+ R(l2 (75 -500) (265 1000))
864
+ )
865
+ T(B
866
+ R(l3 (-75 -500) (150 1000))
867
+ )
868
+ )
869
+ D(D$pfet_01v8_hvt$57 pfet_01v8_hvt
870
+ T(S
871
+ R(l2 (-340 -210) (265 420))
872
+ )
873
+ T(G
874
+ R(l4 (-75 -210) (150 420))
875
+ )
876
+ T(D
877
+ R(l2 (75 -210) (290 420))
878
+ )
879
+ T(B
880
+ R(l3 (-75 -210) (150 420))
881
+ )
882
+ )
883
+ D(D$pfet_01v8_hvt$58 pfet_01v8_hvt
884
+ T(S
885
+ Q(l2 (205 -430) (0 220) (-130 0) (0 420) (620 0) (0 -640))
886
+ )
887
+ T(G
888
+ R(l4 (-75 -210) (150 420))
889
+ )
890
+ T(D
891
+ R(l2 (-365 -210) (290 420))
892
+ )
893
+ T(B
894
+ R(l3 (-75 -210) (150 420))
895
+ )
896
+ )
897
+ D(D$pfet_01v8_hvt$59 pfet_01v8_hvt
898
+ T(S
899
+ Q(l2 (-565 -320) (0 220) (-130 0) (0 420) (620 0) (0 -640))
900
+ )
901
+ T(G
902
+ R(l4 (-75 -320) (150 640))
903
+ )
904
+ T(D
905
+ R(l2 (75 -320) (265 640))
906
+ )
907
+ T(B
908
+ R(l3 (-75 -320) (150 640))
909
+ )
910
+ )
911
+ D(D$pfet_01v8_hvt$60 pfet_01v8_hvt
912
+ T(S
913
+ R(l2 (-345 -500) (270 1000))
914
+ )
915
+ T(G
916
+ R(l4 (-75 -500) (150 1000))
917
+ )
918
+ T(D
919
+ R(l2 (75 -500) (330 1000))
920
+ )
921
+ T(B
922
+ R(l3 (-75 -500) (150 1000))
923
+ )
924
+ )
925
+ D(D$pfet_01v8_hvt$61 pfet_01v8_hvt
926
+ T(S
927
+ R(l2 (-405 -500) (330 1000))
928
+ )
929
+ T(G
930
+ R(l4 (-75 -500) (150 1000))
931
+ )
932
+ T(D
933
+ R(l2 (75 -500) (260 1000))
934
+ )
935
+ T(B
936
+ R(l3 (-75 -500) (150 1000))
937
+ )
938
+ )
939
+ D(D$pfet_01v8_hvt$62 pfet_01v8_hvt
940
+ T(S
941
+ R(l2 (-285 -210) (210 420))
942
+ )
943
+ T(G
944
+ R(l4 (-75 -210) (150 420))
945
+ )
946
+ T(D
947
+ Q(l2 (75 -210) (0 420) (75 0) (0 580) (260 0) (0 -1000))
948
+ )
949
+ T(B
950
+ R(l3 (-75 -210) (150 420))
951
+ )
952
+ )
953
+ D(D$pfet_01v8_hvt$63 pfet_01v8_hvt
954
+ T(S
955
+ Q(l2 (-410 -500) (0 420) (75 0) (0 580) (260 0) (0 -1000))
956
+ )
957
+ T(G
958
+ R(l4 (-75 -500) (150 1000))
959
+ )
960
+ T(D
961
+ R(l2 (75 -500) (340 1000))
962
+ )
963
+ T(B
964
+ R(l3 (-75 -500) (150 1000))
965
+ )
966
+ )
967
+ D(D$pfet_01v8_hvt$64 pfet_01v8_hvt
968
+ T(S
969
+ R(l2 (-345 -500) (270 1000))
970
+ )
971
+ T(G
972
+ R(l4 (-75 -500) (150 1000))
973
+ )
974
+ T(D
975
+ R(l2 (75 -500) (430 1000))
976
+ )
977
+ T(B
978
+ R(l3 (-75 -500) (150 1000))
979
+ )
980
+ )
981
+ D(D$pfet_01v8_hvt$65 pfet_01v8_hvt
982
+ T(S
983
+ R(l2 (-505 -500) (430 1000))
984
+ )
985
+ T(G
986
+ R(l4 (-75 -500) (150 1000))
987
+ )
988
+ T(D
989
+ R(l2 (75 -500) (270 1000))
990
+ )
991
+ T(B
992
+ R(l3 (-75 -500) (150 1000))
993
+ )
994
+ )
995
+ D(D$pfet_01v8_hvt$66 pfet_01v8_hvt
996
+ T(S
997
+ R(l2 (-345 -500) (270 1000))
998
+ )
999
+ T(G
1000
+ R(l4 (-75 -500) (150 1000))
1001
+ )
1002
+ T(D
1003
+ R(l2 (75 -500) (670 1000))
1004
+ )
1005
+ T(B
1006
+ R(l3 (-75 -500) (150 1000))
1007
+ )
1008
+ )
1009
+ D(D$pfet_01v8_hvt$67 pfet_01v8_hvt
1010
+ T(S
1011
+ R(l2 (-745 -500) (670 1000))
1012
+ )
1013
+ T(G
1014
+ R(l4 (-75 -500) (150 1000))
1015
+ )
1016
+ T(D
1017
+ R(l2 (75 -500) (270 1000))
1018
+ )
1019
+ T(B
1020
+ R(l3 (-75 -500) (150 1000))
1021
+ )
1022
+ )
1023
+ D(D$pfet_01v8_hvt$68 pfet_01v8_hvt
1024
+ T(S
1025
+ R(l2 (-345 -500) (270 1000))
1026
+ )
1027
+ T(G
1028
+ R(l4 (-75 -500) (150 1000))
1029
+ )
1030
+ T(D
1031
+ R(l2 (75 -500) (420 1000))
1032
+ )
1033
+ T(B
1034
+ R(l3 (-75 -500) (150 1000))
1035
+ )
1036
+ )
1037
+ D(D$pfet_01v8_hvt$69 pfet_01v8_hvt
1038
+ T(S
1039
+ Q(l2 (-325 -500) (0 710) (-10 0) (0 290) (260 0) (0 -1000))
1040
+ )
1041
+ T(G
1042
+ R(l4 (-75 -500) (150 1000))
1043
+ )
1044
+ T(D
1045
+ R(l2 (75 -500) (320 1000))
1046
+ )
1047
+ T(B
1048
+ R(l3 (-75 -500) (150 1000))
1049
+ )
1050
+ )
1051
+ D(D$pfet_01v8_hvt$70 pfet_01v8_hvt
1052
+ T(S
1053
+ R(l2 (-395 -500) (320 1000))
1054
+ )
1055
+ T(G
1056
+ R(l4 (-75 -500) (150 1000))
1057
+ )
1058
+ T(D
1059
+ R(l2 (75 -500) (310 1000))
1060
+ )
1061
+ T(B
1062
+ R(l3 (-75 -500) (150 1000))
1063
+ )
1064
+ )
1065
+ D(D$pfet_01v8_hvt$71 pfet_01v8_hvt
1066
+ T(S
1067
+ R(l2 (-385 -500) (310 1000))
1068
+ )
1069
+ T(G
1070
+ R(l4 (-75 -500) (150 1000))
1071
+ )
1072
+ T(D
1073
+ R(l2 (75 -500) (260 1000))
1074
+ )
1075
+ T(B
1076
+ R(l3 (-75 -500) (150 1000))
1077
+ )
1078
+ )
1079
+ D(D$pfet_01v8_hvt$72 pfet_01v8_hvt
1080
+ T(S
1081
+ R(l2 (-345 -500) (270 1000))
1082
+ )
1083
+ T(G
1084
+ R(l4 (-75 -500) (150 1000))
1085
+ )
1086
+ T(D
1087
+ Q(l2 (75 -500) (0 1000) (250 0) (0 -715) (10 0) (0 -285))
1088
+ )
1089
+ T(B
1090
+ R(l3 (-75 -500) (150 1000))
1091
+ )
1092
+ )
1093
+ D(D$pfet_01v8_hvt$73 pfet_01v8_hvt
1094
+ T(S
1095
+ R(l2 (-345 -500) (270 1000))
1096
+ )
1097
+ T(G
1098
+ R(l4 (-75 -500) (150 1000))
1099
+ )
1100
+ T(D
1101
+ R(l2 (75 -500) (300 1000))
1102
+ )
1103
+ T(B
1104
+ R(l3 (-75 -500) (150 1000))
1105
+ )
1106
+ )
1107
+ D(D$pfet_01v8_hvt$74 pfet_01v8_hvt
1108
+ T(S
1109
+ R(l2 (-345 -500) (270 1000))
1110
+ )
1111
+ T(G
1112
+ R(l4 (-75 -500) (150 1000))
1113
+ )
1114
+ T(D
1115
+ R(l2 (75 -500) (305 1000))
1116
+ )
1117
+ T(B
1118
+ R(l3 (-75 -500) (150 1000))
1119
+ )
1120
+ )
1121
+ D(D$pfet_01v8_hvt$75 pfet_01v8_hvt
1122
+ T(S
1123
+ R(l2 (-380 -500) (305 1000))
1124
+ )
1125
+ T(G
1126
+ R(l4 (-75 -500) (150 1000))
1127
+ )
1128
+ T(D
1129
+ R(l2 (75 -500) (325 1000))
1130
+ )
1131
+ T(B
1132
+ R(l3 (-75 -500) (150 1000))
1133
+ )
1134
+ )
1135
+ D(D$pfet_01v8_hvt$76 pfet_01v8_hvt
1136
+ T(S
1137
+ R(l2 (-400 -500) (325 1000))
1138
+ )
1139
+ T(G
1140
+ R(l4 (-75 -500) (150 1000))
1141
+ )
1142
+ T(D
1143
+ R(l2 (75 -500) (270 1000))
1144
+ )
1145
+ T(B
1146
+ R(l3 (-75 -500) (150 1000))
1147
+ )
1148
+ )
1149
+ D(D$pfet_01v8_hvt$77 pfet_01v8_hvt
1150
+ T(S
1151
+ R(l2 (-340 -500) (265 1000))
1152
+ )
1153
+ T(G
1154
+ R(l4 (-75 -500) (150 1000))
1155
+ )
1156
+ T(D
1157
+ R(l2 (75 -500) (210 1000))
1158
+ )
1159
+ T(B
1160
+ R(l3 (-75 -500) (150 1000))
1161
+ )
1162
+ )
1163
+ D(D$pfet_01v8_hvt$78 pfet_01v8_hvt
1164
+ T(S
1165
+ R(l2 (-285 -500) (210 1000))
1166
+ )
1167
+ T(G
1168
+ R(l4 (-75 -500) (150 1000))
1169
+ )
1170
+ T(D
1171
+ R(l2 (75 -500) (390 1000))
1172
+ )
1173
+ T(B
1174
+ R(l3 (-75 -500) (150 1000))
1175
+ )
1176
+ )
1177
+ D(D$pfet_01v8_hvt$79 pfet_01v8_hvt
1178
+ T(S
1179
+ R(l2 (-465 -500) (390 1000))
1180
+ )
1181
+ T(G
1182
+ R(l4 (-75 -500) (150 1000))
1183
+ )
1184
+ T(D
1185
+ R(l2 (75 -500) (390 1000))
1186
+ )
1187
+ T(B
1188
+ R(l3 (-75 -500) (150 1000))
1189
+ )
1190
+ )
1191
+ D(D$pfet_01v8_hvt$80 pfet_01v8_hvt
1192
+ T(S
1193
+ R(l2 (-465 -500) (390 1000))
1194
+ )
1195
+ T(G
1196
+ R(l4 (-75 -500) (150 1000))
1197
+ )
1198
+ T(D
1199
+ R(l2 (75 -500) (635 1000))
1200
+ )
1201
+ T(B
1202
+ R(l3 (-75 -500) (150 1000))
1203
+ )
1204
+ )
1205
+ D(D$pfet_01v8_hvt$81 pfet_01v8_hvt
1206
+ T(S
1207
+ Q(l2 (-410 -375) (0 1000) (260 0) (0 -415) (75 0) (0 -420) (-75 0) (0 -165))
1208
+ )
1209
+ T(G
1210
+ R(l4 (-75 -210) (150 420))
1211
+ )
1212
+ T(D
1213
+ R(l2 (75 -210) (260 420))
1214
+ )
1215
+ T(B
1216
+ R(l3 (-75 -210) (150 420))
1217
+ )
1218
+ )
1219
+ D(D$pfet_01v8_hvt$82 pfet_01v8_hvt
1220
+ T(S
1221
+ R(l2 (-345 -500) (270 1000))
1222
+ )
1223
+ T(G
1224
+ R(l4 (-75 -500) (150 1000))
1225
+ )
1226
+ T(D
1227
+ Q(l2 (75 -500) (0 1000) (260 0) (0 -415) (75 0) (0 -420) (-75 0) (0 -165))
1228
+ )
1229
+ T(B
1230
+ R(l3 (-75 -500) (150 1000))
1231
+ )
1232
+ )
1233
+ D(D$pfet_01v8_hvt$83 pfet_01v8_hvt
1234
+ T(S
1235
+ R(l2 (-285 -500) (210 1000))
1236
+ )
1237
+ T(G
1238
+ R(l4 (-75 -500) (150 1000))
1239
+ )
1240
+ T(D
1241
+ Q(l2 (75 -500) (0 1000) (390 0) (0 -700) (-140 0) (0 -300))
1242
+ )
1243
+ T(B
1244
+ R(l3 (-75 -500) (150 1000))
1245
+ )
1246
+ )
1247
+ D(D$pfet_01v8_hvt$84 pfet_01v8_hvt
1248
+ T(S
1249
+ Q(l2 (-465 -650) (0 1000) (390 0) (0 -700) (-140 0) (0 -300))
1250
+ )
1251
+ T(G
1252
+ R(l4 (-75 -350) (150 700))
1253
+ )
1254
+ T(D
1255
+ R(l2 (75 -350) (260 700))
1256
+ )
1257
+ T(B
1258
+ R(l3 (-75 -350) (150 700))
1259
+ )
1260
+ )
1261
+ D(D$pfet_01v8_hvt$85 pfet_01v8_hvt
1262
+ T(S
1263
+ R(l2 (-345 -500) (270 1000))
1264
+ )
1265
+ T(G
1266
+ R(l4 (-75 -500) (150 1000))
1267
+ )
1268
+ T(D
1269
+ R(l2 (75 -500) (820 1000))
1270
+ )
1271
+ T(B
1272
+ R(l3 (-75 -500) (150 1000))
1273
+ )
1274
+ )
1275
+ D(D$pfet_01v8_hvt$86 pfet_01v8_hvt
1276
+ T(S
1277
+ R(l2 (-895 -500) (820 1000))
1278
+ )
1279
+ T(G
1280
+ R(l4 (-75 -500) (150 1000))
1281
+ )
1282
+ T(D
1283
+ R(l2 (75 -500) (360 1000))
1284
+ )
1285
+ T(B
1286
+ R(l3 (-75 -500) (150 1000))
1287
+ )
1288
+ )
1289
+ D(D$pfet_01v8_hvt$87 pfet_01v8_hvt
1290
+ T(S
1291
+ R(l2 (-435 -500) (360 1000))
1292
+ )
1293
+ T(G
1294
+ R(l4 (-75 -500) (150 1000))
1295
+ )
1296
+ T(D
1297
+ R(l2 (75 -500) (350 1000))
1298
+ )
1299
+ T(B
1300
+ R(l3 (-75 -500) (150 1000))
1301
+ )
1302
+ )
1303
+ D(D$pfet_01v8_hvt$88 pfet_01v8_hvt
1304
+ T(S
1305
+ R(l2 (-425 -500) (350 1000))
1306
+ )
1307
+ T(G
1308
+ R(l4 (-75 -500) (150 1000))
1309
+ )
1310
+ T(D
1311
+ R(l2 (75 -500) (260 1000))
1312
+ )
1313
+ T(B
1314
+ R(l3 (-75 -500) (150 1000))
1315
+ )
1316
+ )
1317
+ D(D$pfet_01v8_hvt$89 pfet_01v8_hvt
1318
+ T(S
1319
+ R(l2 (-335 -500) (260 1000))
1320
+ )
1321
+ T(G
1322
+ R(l4 (-75 -500) (150 1000))
1323
+ )
1324
+ T(D
1325
+ R(l2 (75 -500) (260 1000))
1326
+ )
1327
+ T(B
1328
+ R(l3 (-75 -500) (150 1000))
1329
+ )
1330
+ )
1331
+ D(D$pfet_01v8_hvt$90 pfet_01v8_hvt
1332
+ T(S
1333
+ R(l2 (-285 -210) (210 420))
1334
+ )
1335
+ T(G
1336
+ R(l4 (-75 -210) (150 420))
1337
+ )
1338
+ T(D
1339
+ R(l2 (75 -210) (330 420))
1340
+ )
1341
+ T(B
1342
+ R(l3 (-75 -210) (150 420))
1343
+ )
1344
+ )
1345
+ D(D$pfet_01v8_hvt$91 pfet_01v8_hvt
1346
+ T(S
1347
+ R(l2 (-405 -210) (330 420))
1348
+ )
1349
+ T(G
1350
+ R(l4 (-75 -210) (150 420))
1351
+ )
1352
+ T(D
1353
+ Q(l2 (75 -210) (0 420) (75 0) (0 580) (265 0) (0 -1000))
1354
+ )
1355
+ T(B
1356
+ R(l3 (-75 -210) (150 420))
1357
+ )
1358
+ )
1359
+ D(D$pfet_01v8_hvt$92 pfet_01v8_hvt
1360
+ T(S
1361
+ Q(l2 (-415 -500) (0 420) (75 0) (0 580) (265 0) (0 -1000))
1362
+ )
1363
+ T(G
1364
+ R(l4 (-75 -500) (150 1000))
1365
+ )
1366
+ T(D
1367
+ R(l2 (75 -500) (280 1000))
1368
+ )
1369
+ T(B
1370
+ R(l3 (-75 -500) (150 1000))
1371
+ )
1372
+ )
1373
+ D(D$pfet_01v8_hvt$93 pfet_01v8_hvt
1374
+ T(S
1375
+ R(l2 (-340 -320) (265 640))
1376
+ )
1377
+ T(G
1378
+ R(l4 (-75 -320) (150 640))
1379
+ )
1380
+ T(D
1381
+ R(l2 (75 -320) (240 640))
1382
+ )
1383
+ T(B
1384
+ R(l3 (-75 -320) (150 640))
1385
+ )
1386
+ )
1387
+ D(D$pfet_01v8_hvt$94 pfet_01v8_hvt
1388
+ T(S
1389
+ R(l2 (-315 -320) (240 640))
1390
+ )
1391
+ T(G
1392
+ R(l4 (-75 -320) (150 640))
1393
+ )
1394
+ T(D
1395
+ R(l2 (75 -320) (280 640))
1396
+ )
1397
+ T(B
1398
+ R(l3 (-75 -320) (150 640))
1399
+ )
1400
+ )
1401
+ D(D$pfet_01v8_hvt$95 pfet_01v8_hvt
1402
+ T(S
1403
+ R(l2 (-355 -320) (280 640))
1404
+ )
1405
+ T(G
1406
+ R(l4 (-75 -320) (150 640))
1407
+ )
1408
+ T(D
1409
+ R(l2 (75 -320) (285 640))
1410
+ )
1411
+ T(B
1412
+ R(l3 (-75 -320) (150 640))
1413
+ )
1414
+ )
1415
+ D(D$nfet_01v8 nfet_01v8
1416
+ T(S
1417
+ R(l8 (-335 -210) (260 420))
1418
+ )
1419
+ T(G
1420
+ R(l4 (-75 -210) (150 420))
1421
+ )
1422
+ T(D
1423
+ R(l8 (75 -210) (210 420))
1424
+ )
1425
+ T(B
1426
+ R(l9 (-75 -210) (150 420))
1427
+ )
1428
+ )
1429
+ D(D$nfet_01v8$1 nfet_01v8
1430
+ T(S
1431
+ R(l8 (-285 -210) (210 420))
1432
+ )
1433
+ T(G
1434
+ R(l4 (-75 -210) (150 420))
1435
+ )
1436
+ T(D
1437
+ R(l8 (75 -210) (270 420))
1438
+ )
1439
+ T(B
1440
+ R(l9 (-75 -210) (150 420))
1441
+ )
1442
+ )
1443
+ D(D$nfet_01v8$2 nfet_01v8
1444
+ T(S
1445
+ R(l8 (-345 -210) (270 420))
1446
+ )
1447
+ T(G
1448
+ R(l4 (-75 -210) (150 420))
1449
+ )
1450
+ T(D
1451
+ R(l8 (75 -210) (210 420))
1452
+ )
1453
+ T(B
1454
+ R(l9 (-75 -210) (150 420))
1455
+ )
1456
+ )
1457
+ D(D$nfet_01v8$3 nfet_01v8
1458
+ T(S
1459
+ R(l8 (-285 -210) (210 420))
1460
+ )
1461
+ T(G
1462
+ R(l4 (-75 -210) (150 420))
1463
+ )
1464
+ T(D
1465
+ Q(l8 (75 -210) (0 420) (315 0) (0 230) (250 0) (0 -650))
1466
+ )
1467
+ T(B
1468
+ R(l9 (-75 -210) (150 420))
1469
+ )
1470
+ )
1471
+ D(D$nfet_01v8$4 nfet_01v8
1472
+ T(S
1473
+ Q(l8 (-640 -325) (0 420) (315 0) (0 230) (250 0) (0 -650))
1474
+ )
1475
+ T(G
1476
+ R(l4 (-75 -325) (150 650))
1477
+ )
1478
+ T(D
1479
+ R(l8 (75 -325) (365 650))
1480
+ )
1481
+ T(B
1482
+ R(l9 (-75 -325) (150 650))
1483
+ )
1484
+ )
1485
+ D(D$nfet_01v8$5 nfet_01v8
1486
+ T(S
1487
+ R(l8 (-335 -325) (260 650))
1488
+ )
1489
+ T(G
1490
+ R(l4 (-75 -325) (150 650))
1491
+ )
1492
+ T(D
1493
+ R(l8 (75 -325) (270 650))
1494
+ )
1495
+ T(B
1496
+ R(l9 (-75 -325) (150 650))
1497
+ )
1498
+ )
1499
+ D(D$nfet_01v8$6 nfet_01v8
1500
+ T(S
1501
+ R(l8 (-345 -325) (270 650))
1502
+ )
1503
+ T(G
1504
+ R(l4 (-75 -325) (150 650))
1505
+ )
1506
+ T(D
1507
+ R(l8 (75 -325) (260 650))
1508
+ )
1509
+ T(B
1510
+ R(l9 (-75 -325) (150 650))
1511
+ )
1512
+ )
1513
+ D(D$nfet_01v8$7 nfet_01v8
1514
+ T(S
1515
+ Q(l8 (-680 -210) (0 640) (500 0) (0 -220) (105 0) (0 -420))
1516
+ )
1517
+ T(G
1518
+ R(l4 (-75 -210) (150 420))
1519
+ )
1520
+ T(D
1521
+ Q(l8 (75 -210) (0 420) (125 0) (0 220) (520 0) (0 -640))
1522
+ )
1523
+ T(B
1524
+ R(l9 (-75 -210) (150 420))
1525
+ )
1526
+ )
1527
+ D(D$nfet_01v8$8 nfet_01v8
1528
+ T(S
1529
+ Q(l8 (-440 -300) (0 10) (-85 0) (0 640) (250 0) (0 -50) (200 0) (0 -600))
1530
+ )
1531
+ T(G
1532
+ R(l4 (-75 -300) (150 600))
1533
+ )
1534
+ T(D
1535
+ Q(l8 (75 -300) (0 600) (100 0) (0 40) (250 0) (0 -640))
1536
+ )
1537
+ T(B
1538
+ R(l9 (-75 -300) (150 600))
1539
+ )
1540
+ )
1541
+ D(D$nfet_01v8$9 nfet_01v8
1542
+ T(S
1543
+ Q(l8 (-425 -320) (0 600) (100 0) (0 40) (250 0) (0 -640))
1544
+ )
1545
+ T(G
1546
+ R(l4 (-75 -320) (150 640))
1547
+ )
1548
+ T(D
1549
+ R(l8 (75 -320) (270 640))
1550
+ )
1551
+ T(B
1552
+ R(l9 (-75 -320) (150 640))
1553
+ )
1554
+ )
1555
+ D(D$nfet_01v8$10 nfet_01v8
1556
+ T(S
1557
+ R(l8 (-345 -320) (270 640))
1558
+ )
1559
+ T(G
1560
+ R(l4 (-75 -320) (150 640))
1561
+ )
1562
+ T(D
1563
+ R(l8 (75 -320) (285 640))
1564
+ )
1565
+ T(B
1566
+ R(l9 (-75 -320) (150 640))
1567
+ )
1568
+ )
1569
+ D(D$nfet_01v8$11 nfet_01v8
1570
+ T(S
1571
+ Q(l8 (-335 -320) (0 275) (10 0) (0 365) (250 0) (0 -640))
1572
+ )
1573
+ T(G
1574
+ R(l4 (-75 -320) (150 640))
1575
+ )
1576
+ T(D
1577
+ Q(l8 (75 -320) (0 640) (500 0) (0 -220) (105 0) (0 -420))
1578
+ )
1579
+ T(B
1580
+ R(l9 (-75 -320) (150 640))
1581
+ )
1582
+ )
1583
+ D(D$nfet_01v8$12 nfet_01v8
1584
+ T(S
1585
+ Q(l8 (160 -330) (0 10) (-85 0) (0 640) (250 0) (0 -50) (200 0) (0 -600))
1586
+ )
1587
+ T(G
1588
+ R(l4 (-75 -320) (150 640))
1589
+ )
1590
+ T(D
1591
+ Q(l8 (-720 -320) (0 420) (125 0) (0 220) (520 0) (0 -640))
1592
+ )
1593
+ T(B
1594
+ R(l9 (-75 -320) (150 640))
1595
+ )
1596
+ )
1597
+ D(D$nfet_01v8$13 nfet_01v8
1598
+ T(S
1599
+ R(l8 (-335 -325) (260 650))
1600
+ )
1601
+ T(G
1602
+ R(l4 (-75 -325) (150 650))
1603
+ )
1604
+ T(D
1605
+ Q(l8 (75 -325) (0 650) (385 0) (0 -420) (-75 0) (0 -230))
1606
+ )
1607
+ T(B
1608
+ R(l9 (-75 -325) (150 650))
1609
+ )
1610
+ )
1611
+ D(D$nfet_01v8$14 nfet_01v8
1612
+ T(S
1613
+ Q(l8 (-460 -440) (0 650) (385 0) (0 -420) (-75 0) (0 -230))
1614
+ )
1615
+ T(G
1616
+ R(l4 (-75 -210) (150 420))
1617
+ )
1618
+ T(D
1619
+ R(l8 (75 -210) (425 420))
1620
+ )
1621
+ T(B
1622
+ R(l9 (-75 -210) (150 420))
1623
+ )
1624
+ )
1625
+ D(D$nfet_01v8$15 nfet_01v8
1626
+ T(S
1627
+ R(l8 (-345 -320) (270 640))
1628
+ )
1629
+ T(G
1630
+ R(l4 (-75 -320) (150 640))
1631
+ )
1632
+ T(D
1633
+ R(l8 (75 -320) (290 640))
1634
+ )
1635
+ T(B
1636
+ R(l9 (-75 -320) (150 640))
1637
+ )
1638
+ )
1639
+ D(D$nfet_01v8$16 nfet_01v8
1640
+ T(S
1641
+ R(l8 (-365 -320) (290 640))
1642
+ )
1643
+ T(G
1644
+ R(l4 (-75 -320) (150 640))
1645
+ )
1646
+ T(D
1647
+ R(l8 (75 -320) (350 640))
1648
+ )
1649
+ T(B
1650
+ R(l9 (-75 -320) (150 640))
1651
+ )
1652
+ )
1653
+ D(D$nfet_01v8$17 nfet_01v8
1654
+ T(S
1655
+ R(l8 (-365 -325) (290 650))
1656
+ )
1657
+ T(G
1658
+ R(l4 (-75 -325) (150 650))
1659
+ )
1660
+ T(D
1661
+ Q(l8 (75 -325) (0 650) (260 0) (0 -265) (-10 0) (0 -385))
1662
+ )
1663
+ T(B
1664
+ R(l9 (-75 -325) (150 650))
1665
+ )
1666
+ )
1667
+ D(D$nfet_01v8$18 nfet_01v8
1668
+ T(S
1669
+ R(l8 (-345 -325) (270 650))
1670
+ )
1671
+ T(G
1672
+ R(l4 (-75 -325) (150 650))
1673
+ )
1674
+ T(D
1675
+ R(l8 (75 -325) (270 650))
1676
+ )
1677
+ T(B
1678
+ R(l9 (-75 -325) (150 650))
1679
+ )
1680
+ )
1681
+ D(D$nfet_01v8$19 nfet_01v8
1682
+ T(S
1683
+ R(l8 (-345 -325) (270 650))
1684
+ )
1685
+ T(G
1686
+ R(l4 (-75 -325) (150 650))
1687
+ )
1688
+ T(D
1689
+ R(l8 (75 -325) (770 650))
1690
+ )
1691
+ T(B
1692
+ R(l9 (-75 -325) (150 650))
1693
+ )
1694
+ )
1695
+ D(D$nfet_01v8$20 nfet_01v8
1696
+ T(S
1697
+ R(l8 (-845 -325) (770 650))
1698
+ )
1699
+ T(G
1700
+ R(l4 (-75 -325) (150 650))
1701
+ )
1702
+ T(D
1703
+ R(l8 (75 -325) (320 650))
1704
+ )
1705
+ T(B
1706
+ R(l9 (-75 -325) (150 650))
1707
+ )
1708
+ )
1709
+ D(D$nfet_01v8$21 nfet_01v8
1710
+ T(S
1711
+ R(l8 (-345 -325) (270 650))
1712
+ )
1713
+ T(G
1714
+ R(l4 (-75 -325) (150 650))
1715
+ )
1716
+ T(D
1717
+ R(l8 (75 -325) (300 650))
1718
+ )
1719
+ T(B
1720
+ R(l9 (-75 -325) (150 650))
1721
+ )
1722
+ )
1723
+ D(D$nfet_01v8$22 nfet_01v8
1724
+ T(S
1725
+ R(l8 (-335 -325) (260 650))
1726
+ )
1727
+ T(G
1728
+ R(l4 (-75 -325) (150 650))
1729
+ )
1730
+ T(D
1731
+ R(l8 (75 -325) (210 650))
1732
+ )
1733
+ T(B
1734
+ R(l9 (-75 -325) (150 650))
1735
+ )
1736
+ )
1737
+ D(D$nfet_01v8$23 nfet_01v8
1738
+ T(S
1739
+ R(l8 (-285 -325) (210 650))
1740
+ )
1741
+ T(G
1742
+ R(l4 (-75 -325) (150 650))
1743
+ )
1744
+ T(D
1745
+ R(l8 (75 -325) (270 650))
1746
+ )
1747
+ T(B
1748
+ R(l9 (-75 -325) (150 650))
1749
+ )
1750
+ )
1751
+ D(D$nfet_01v8$24 nfet_01v8
1752
+ T(S
1753
+ Q(l8 (-685 -210) (0 640) (505 0) (0 -220) (105 0) (0 -420))
1754
+ )
1755
+ T(G
1756
+ R(l4 (-75 -210) (150 420))
1757
+ )
1758
+ T(D
1759
+ Q(l8 (75 -210) (0 420) (125 0) (0 220) (520 0) (0 -640))
1760
+ )
1761
+ T(B
1762
+ R(l9 (-75 -210) (150 420))
1763
+ )
1764
+ )
1765
+ D(D$nfet_01v8$25 nfet_01v8
1766
+ T(S
1767
+ Q(l8 (-335 -320) (0 280) (10 0) (0 360) (250 0) (0 -640))
1768
+ )
1769
+ T(G
1770
+ R(l4 (-75 -320) (150 640))
1771
+ )
1772
+ T(D
1773
+ Q(l8 (75 -320) (0 640) (505 0) (0 -220) (105 0) (0 -420))
1774
+ )
1775
+ T(B
1776
+ R(l9 (-75 -320) (150 640))
1777
+ )
1778
+ )
1779
+ D(D$nfet_01v8$26 nfet_01v8
1780
+ T(S
1781
+ R(l8 (-375 -325) (300 650))
1782
+ )
1783
+ T(G
1784
+ R(l4 (-75 -325) (150 650))
1785
+ )
1786
+ T(D
1787
+ Q(l8 (75 -325) (0 650) (260 0) (0 -280) (-10 0) (0 -370))
1788
+ )
1789
+ T(B
1790
+ R(l9 (-75 -325) (150 650))
1791
+ )
1792
+ )
1793
+ D(D$nfet_01v8$27 nfet_01v8
1794
+ T(S
1795
+ R(l8 (-335 -325) (260 650))
1796
+ )
1797
+ T(G
1798
+ R(l4 (-75 -325) (150 650))
1799
+ )
1800
+ T(D
1801
+ Q(l8 (75 -325) (0 650) (470 0) (0 -420) (-75 0) (0 -230))
1802
+ )
1803
+ T(B
1804
+ R(l9 (-75 -325) (150 650))
1805
+ )
1806
+ )
1807
+ D(D$nfet_01v8$28 nfet_01v8
1808
+ T(S
1809
+ Q(l8 (-545 -440) (0 650) (470 0) (0 -420) (-75 0) (0 -230))
1810
+ )
1811
+ T(G
1812
+ R(l4 (-75 -210) (150 420))
1813
+ )
1814
+ T(D
1815
+ R(l8 (75 -210) (420 420))
1816
+ )
1817
+ T(B
1818
+ R(l9 (-75 -210) (150 420))
1819
+ )
1820
+ )
1821
+ D(D$nfet_01v8$29 nfet_01v8
1822
+ T(S
1823
+ R(l8 (-345 -320) (270 640))
1824
+ )
1825
+ T(G
1826
+ R(l4 (-75 -320) (150 640))
1827
+ )
1828
+ T(D
1829
+ R(l8 (75 -320) (400 640))
1830
+ )
1831
+ T(B
1832
+ R(l9 (-75 -320) (150 640))
1833
+ )
1834
+ )
1835
+ D(D$nfet_01v8$30 nfet_01v8
1836
+ T(S
1837
+ R(l8 (-475 -320) (400 640))
1838
+ )
1839
+ T(G
1840
+ R(l4 (-75 -320) (150 640))
1841
+ )
1842
+ T(D
1843
+ R(l8 (75 -320) (495 640))
1844
+ )
1845
+ T(B
1846
+ R(l9 (-75 -320) (150 640))
1847
+ )
1848
+ )
1849
+ D(D$nfet_01v8$31 nfet_01v8
1850
+ T(S
1851
+ R(l8 (-335 -210) (260 420))
1852
+ )
1853
+ T(G
1854
+ R(l4 (-75 -210) (150 420))
1855
+ )
1856
+ T(D
1857
+ R(l8 (75 -210) (285 420))
1858
+ )
1859
+ T(B
1860
+ R(l9 (-75 -210) (150 420))
1861
+ )
1862
+ )
1863
+ D(D$nfet_01v8$32 nfet_01v8
1864
+ T(S
1865
+ R(l8 (-340 -325) (265 650))
1866
+ )
1867
+ T(G
1868
+ R(l4 (-75 -325) (150 650))
1869
+ )
1870
+ T(D
1871
+ R(l8 (75 -325) (280 650))
1872
+ )
1873
+ T(B
1874
+ R(l9 (-75 -325) (150 650))
1875
+ )
1876
+ )
1877
+ D(D$nfet_01v8$33 nfet_01v8
1878
+ T(S
1879
+ R(l8 (-355 -325) (280 650))
1880
+ )
1881
+ T(G
1882
+ R(l4 (-75 -325) (150 650))
1883
+ )
1884
+ T(D
1885
+ R(l8 (75 -325) (295 650))
1886
+ )
1887
+ T(B
1888
+ R(l9 (-75 -325) (150 650))
1889
+ )
1890
+ )
1891
+ D(D$nfet_01v8$34 nfet_01v8
1892
+ T(S
1893
+ R(l8 (-370 -325) (295 650))
1894
+ )
1895
+ T(G
1896
+ R(l4 (-75 -325) (150 650))
1897
+ )
1898
+ T(D
1899
+ R(l8 (75 -325) (265 650))
1900
+ )
1901
+ T(B
1902
+ R(l9 (-75 -325) (150 650))
1903
+ )
1904
+ )
1905
+ D(D$nfet_01v8$35 nfet_01v8
1906
+ T(S
1907
+ R(l8 (-485 -325) (410 650))
1908
+ )
1909
+ T(G
1910
+ R(l4 (-75 -325) (150 650))
1911
+ )
1912
+ T(D
1913
+ R(l8 (75 -325) (280 650))
1914
+ )
1915
+ T(B
1916
+ R(l9 (-75 -325) (150 650))
1917
+ )
1918
+ )
1919
+ D(D$nfet_01v8$36 nfet_01v8
1920
+ T(S
1921
+ R(l8 (-355 -325) (280 650))
1922
+ )
1923
+ T(G
1924
+ R(l4 (-75 -325) (150 650))
1925
+ )
1926
+ T(D
1927
+ R(l8 (75 -325) (280 650))
1928
+ )
1929
+ T(B
1930
+ R(l9 (-75 -325) (150 650))
1931
+ )
1932
+ )
1933
+ D(D$nfet_01v8$37 nfet_01v8
1934
+ T(S
1935
+ R(l8 (-355 -325) (280 650))
1936
+ )
1937
+ T(G
1938
+ R(l4 (-75 -325) (150 650))
1939
+ )
1940
+ T(D
1941
+ R(l8 (75 -325) (310 650))
1942
+ )
1943
+ T(B
1944
+ R(l9 (-75 -325) (150 650))
1945
+ )
1946
+ )
1947
+ D(D$nfet_01v8$38 nfet_01v8
1948
+ T(S
1949
+ R(l8 (-385 -325) (310 650))
1950
+ )
1951
+ T(G
1952
+ R(l4 (-75 -325) (150 650))
1953
+ )
1954
+ T(D
1955
+ R(l8 (75 -325) (265 650))
1956
+ )
1957
+ T(B
1958
+ R(l9 (-75 -325) (150 650))
1959
+ )
1960
+ )
1961
+ D(D$nfet_01v8$39 nfet_01v8
1962
+ T(S
1963
+ R(l8 (-335 -210) (260 420))
1964
+ )
1965
+ T(G
1966
+ R(l4 (-75 -210) (150 420))
1967
+ )
1968
+ T(D
1969
+ Q(l8 (75 -210) (0 420) (75 0) (0 230) (260 0) (0 -650))
1970
+ )
1971
+ T(B
1972
+ R(l9 (-75 -210) (150 420))
1973
+ )
1974
+ )
1975
+ D(D$nfet_01v8$40 nfet_01v8
1976
+ T(S
1977
+ Q(l8 (-410 -325) (0 420) (75 0) (0 230) (260 0) (0 -650))
1978
+ )
1979
+ T(G
1980
+ R(l4 (-75 -325) (150 650))
1981
+ )
1982
+ T(D
1983
+ R(l8 (75 -325) (270 650))
1984
+ )
1985
+ T(B
1986
+ R(l9 (-75 -325) (150 650))
1987
+ )
1988
+ )
1989
+ D(D$nfet_01v8$41 nfet_01v8
1990
+ T(S
1991
+ R(l8 (-335 -325) (260 650))
1992
+ )
1993
+ T(G
1994
+ R(l4 (-75 -325) (150 650))
1995
+ )
1996
+ T(D
1997
+ R(l8 (75 -325) (310 650))
1998
+ )
1999
+ T(B
2000
+ R(l9 (-75 -325) (150 650))
2001
+ )
2002
+ )
2003
+ D(D$nfet_01v8$42 nfet_01v8
2004
+ T(S
2005
+ R(l8 (-385 -325) (310 650))
2006
+ )
2007
+ T(G
2008
+ R(l4 (-75 -325) (150 650))
2009
+ )
2010
+ T(D
2011
+ R(l8 (75 -325) (270 650))
2012
+ )
2013
+ T(B
2014
+ R(l9 (-75 -325) (150 650))
2015
+ )
2016
+ )
2017
+ D(D$nfet_01v8$43 nfet_01v8
2018
+ T(S
2019
+ R(l8 (-335 -325) (260 650))
2020
+ )
2021
+ T(G
2022
+ R(l4 (-75 -325) (150 650))
2023
+ )
2024
+ T(D
2025
+ R(l8 (75 -325) (260 650))
2026
+ )
2027
+ T(B
2028
+ R(l9 (-75 -325) (150 650))
2029
+ )
2030
+ )
2031
+ D(D$nfet_01v8$44 nfet_01v8
2032
+ T(S
2033
+ Q(l8 (150 -440) (0 230) (-75 0) (0 420) (335 0) (0 -650))
2034
+ )
2035
+ T(G
2036
+ R(l4 (-75 -210) (150 420))
2037
+ )
2038
+ T(D
2039
+ R(l8 (-335 -210) (260 420))
2040
+ )
2041
+ T(B
2042
+ R(l9 (-75 -210) (150 420))
2043
+ )
2044
+ )
2045
+ D(D$nfet_01v8$45 nfet_01v8
2046
+ T(S
2047
+ Q(l8 (-335 -325) (0 230) (-75 0) (0 420) (335 0) (0 -650))
2048
+ )
2049
+ T(G
2050
+ R(l4 (-75 -325) (150 650))
2051
+ )
2052
+ T(D
2053
+ R(l8 (75 -325) (270 650))
2054
+ )
2055
+ T(B
2056
+ R(l9 (-75 -325) (150 650))
2057
+ )
2058
+ )
2059
+ D(D$nfet_01v8$46 nfet_01v8
2060
+ T(S
2061
+ R(l8 (-375 -325) (300 650))
2062
+ )
2063
+ T(G
2064
+ R(l4 (-75 -325) (150 650))
2065
+ )
2066
+ T(D
2067
+ R(l8 (75 -325) (270 650))
2068
+ )
2069
+ T(B
2070
+ R(l9 (-75 -325) (150 650))
2071
+ )
2072
+ )
2073
+ D(D$nfet_01v8$47 nfet_01v8
2074
+ T(S
2075
+ R(l8 (-345 -325) (270 650))
2076
+ )
2077
+ T(G
2078
+ R(l4 (-75 -325) (150 650))
2079
+ )
2080
+ T(D
2081
+ Q(l8 (75 -325) (0 650) (385 0) (0 -420) (-75 0) (0 -230))
2082
+ )
2083
+ T(B
2084
+ R(l9 (-75 -325) (150 650))
2085
+ )
2086
+ )
2087
+ D(D$nfet_01v8$48 nfet_01v8
2088
+ T(S
2089
+ R(l8 (-355 -325) (280 650))
2090
+ )
2091
+ T(G
2092
+ R(l4 (-75 -325) (150 650))
2093
+ )
2094
+ T(D
2095
+ R(l8 (75 -325) (390 650))
2096
+ )
2097
+ T(B
2098
+ R(l9 (-75 -325) (150 650))
2099
+ )
2100
+ )
2101
+ D(D$nfet_01v8$49 nfet_01v8
2102
+ T(S
2103
+ R(l8 (-465 -325) (390 650))
2104
+ )
2105
+ T(G
2106
+ R(l4 (-75 -325) (150 650))
2107
+ )
2108
+ T(D
2109
+ R(l8 (75 -325) (280 650))
2110
+ )
2111
+ T(B
2112
+ R(l9 (-75 -325) (150 650))
2113
+ )
2114
+ )
2115
+ D(D$nfet_01v8$50 nfet_01v8
2116
+ T(S
2117
+ R(l8 (-355 -325) (280 650))
2118
+ )
2119
+ T(G
2120
+ R(l4 (-75 -325) (150 650))
2121
+ )
2122
+ T(D
2123
+ R(l8 (75 -325) (265 650))
2124
+ )
2125
+ T(B
2126
+ R(l9 (-75 -325) (150 650))
2127
+ )
2128
+ )
2129
+ D(D$nfet_01v8$51 nfet_01v8
2130
+ T(S
2131
+ R(l8 (-340 -210) (265 420))
2132
+ )
2133
+ T(G
2134
+ R(l4 (-75 -210) (150 420))
2135
+ )
2136
+ T(D
2137
+ R(l8 (75 -210) (210 420))
2138
+ )
2139
+ T(B
2140
+ R(l9 (-75 -210) (150 420))
2141
+ )
2142
+ )
2143
+ D(D$nfet_01v8$52 nfet_01v8
2144
+ T(S
2145
+ R(l8 (-285 -210) (210 420))
2146
+ )
2147
+ T(G
2148
+ R(l4 (-75 -210) (150 420))
2149
+ )
2150
+ T(D
2151
+ R(l8 (75 -210) (460 420))
2152
+ )
2153
+ T(B
2154
+ R(l9 (-75 -210) (150 420))
2155
+ )
2156
+ )
2157
+ D(D$nfet_01v8$53 nfet_01v8
2158
+ T(S
2159
+ R(l8 (-535 -210) (460 420))
2160
+ )
2161
+ T(G
2162
+ R(l4 (-75 -210) (150 420))
2163
+ )
2164
+ T(D
2165
+ R(l8 (75 -210) (265 420))
2166
+ )
2167
+ T(B
2168
+ R(l9 (-75 -210) (150 420))
2169
+ )
2170
+ )
2171
+ D(D$nfet_01v8$54 nfet_01v8
2172
+ T(S
2173
+ R(l8 (-345 -325) (270 650))
2174
+ )
2175
+ T(G
2176
+ R(l4 (-75 -325) (150 650))
2177
+ )
2178
+ T(D
2179
+ R(l8 (75 -325) (330 650))
2180
+ )
2181
+ T(B
2182
+ R(l9 (-75 -325) (150 650))
2183
+ )
2184
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2185
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2186
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2187
+ R(l8 (-405 -325) (330 650))
2188
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2189
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2190
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2191
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2192
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2193
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2194
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2195
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2196
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2197
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2198
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2199
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2200
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2201
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2202
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2204
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2205
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2206
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2207
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2208
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2210
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2211
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2212
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2213
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2214
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2215
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2216
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2217
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2218
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2219
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2220
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2221
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2222
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2223
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2224
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2225
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2226
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2227
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2228
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2229
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2230
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2231
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2232
+ R(l4 (-75 -325) (150 650))
2233
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2234
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2235
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2236
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2237
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2238
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2239
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2240
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2241
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2242
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2243
+ R(l8 (-355 -325) (280 650))
2244
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2245
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2246
+ R(l4 (-75 -325) (150 650))
2247
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2248
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2249
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2250
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2251
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2252
+ R(l9 (-75 -325) (150 650))
2253
+ )
2254
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2255
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2256
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2257
+ R(l8 (-345 -325) (270 650))
2258
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2259
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2260
+ R(l4 (-75 -325) (150 650))
2261
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2262
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2263
+ R(l8 (75 -325) (360 650))
2264
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2265
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2266
+ R(l9 (-75 -325) (150 650))
2267
+ )
2268
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2269
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2270
+ T(S
2271
+ R(l8 (-345 -325) (270 650))
2272
+ )
2273
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2274
+ R(l4 (-75 -325) (150 650))
2275
+ )
2276
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2277
+ R(l8 (75 -325) (280 650))
2278
+ )
2279
+ T(B
2280
+ R(l9 (-75 -325) (150 650))
2281
+ )
2282
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2283
+ D(D$nfet_01v8$62 nfet_01v8
2284
+ T(S
2285
+ R(l8 (-335 -325) (260 650))
2286
+ )
2287
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2288
+ R(l4 (-75 -325) (150 650))
2289
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2290
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2291
+ R(l8 (75 -325) (350 650))
2292
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2293
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2294
+ R(l9 (-75 -325) (150 650))
2295
+ )
2296
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2297
+ D(D$nfet_01v8$63 nfet_01v8
2298
+ T(S
2299
+ R(l8 (-425 -325) (350 650))
2300
+ )
2301
+ T(G
2302
+ R(l4 (-75 -325) (150 650))
2303
+ )
2304
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2305
+ R(l8 (75 -325) (310 650))
2306
+ )
2307
+ T(B
2308
+ R(l9 (-75 -325) (150 650))
2309
+ )
2310
+ )
2311
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2312
+ T(S
2313
+ R(l8 (-385 -325) (310 650))
2314
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2315
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2316
+ R(l4 (-75 -325) (150 650))
2317
+ )
2318
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2319
+ R(l8 (75 -325) (260 650))
2320
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2321
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2322
+ R(l9 (-75 -325) (150 650))
2323
+ )
2324
+ )
2325
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2326
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2327
+ R(l8 (-335 -325) (260 650))
2328
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2329
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2330
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2331
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2332
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2333
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2334
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2335
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2336
+ R(l9 (-75 -325) (150 650))
2337
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2338
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2339
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2340
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2341
+ R(l8 (-305 -325) (230 650))
2342
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2343
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2344
+ R(l4 (-75 -325) (150 650))
2345
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2346
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2347
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2348
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2349
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2350
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2351
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2352
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2353
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2354
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2355
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2356
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2357
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2358
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2359
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2360
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2361
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2362
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2363
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2364
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2365
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2366
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2367
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2368
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2369
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2370
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2371
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2372
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2373
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2374
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2375
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2376
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2377
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2378
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2379
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2380
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2381
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2382
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2383
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2384
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2385
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2386
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2387
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2388
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2389
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2390
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2391
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2392
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2393
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2394
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2395
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2396
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2397
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2398
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2399
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2400
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2401
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2402
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2403
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2404
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2405
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2406
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2407
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2408
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2409
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2410
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2411
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2412
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2413
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2414
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2415
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2416
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2417
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2418
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2419
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2420
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2421
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2422
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2423
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2424
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2425
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2426
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2427
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2428
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2429
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2430
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2431
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2432
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2433
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2434
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2435
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2436
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2437
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2438
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2439
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2440
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2441
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2442
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2443
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2444
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2445
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2446
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2447
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2448
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2449
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2450
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2451
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2452
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2453
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2454
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2455
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2456
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2457
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2458
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2459
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2460
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2461
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2462
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2463
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2464
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2465
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2466
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2467
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2468
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2469
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2470
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2471
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2472
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2473
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2474
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2475
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2476
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2477
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2478
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2479
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2480
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2481
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2482
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2483
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2484
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2485
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2487
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2488
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2490
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2491
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2492
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2493
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2494
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2495
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2496
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2497
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2498
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2499
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2505
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2506
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2507
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2508
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2509
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2510
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2511
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2513
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2516
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2518
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2519
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2520
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2521
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2523
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2524
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2529
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2530
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2532
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2533
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2534
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2535
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2538
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2540
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2546
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2561
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2617
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2619
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2620
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2631
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2632
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2633
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2634
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2635
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2636
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2639
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2640
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2645
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2646
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2647
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2648
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2649
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2650
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2653
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2656
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2659
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2660
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2661
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2663
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2664
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2665
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2670
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2672
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2673
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2674
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2675
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2676
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2677
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2678
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2679
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2680
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2681
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2682
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2683
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2687
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2688
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2690
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2691
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2692
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2693
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2698
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2699
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2700
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2701
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2702
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2703
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2704
+ H(
2705
+ K(NFET_01V8 MOS4)
2706
+ K(PFET_01V8_HVT MOS4)
2707
+ K(RES RES)
2708
+ )
2709
+ Z(
2710
+ )
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