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alu_w32_5ops_sky130_1000mhz/flow/alu_w32_5ops.gds.gz

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+version https://git-lfs.github.com/spec/v1
+oid sha256:b44c80c33d8b903c5be39d8f91fc1aaa0ccc1f0ea2659c1650a1efab451da9b2
+size 113949

alu_w32_5ops_sky130_1000mhz/flow/alu_w32_5ops.spef.gz

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+version https://git-lfs.github.com/spec/v1
+oid sha256:4674a20fc278e13fbf23f64a2c1c82a444ac1bd30a632a7d37b796f1bd2f8991
+size 142990

alu_w32_5ops_sky130_1000mhz/flow/clean_gds_for_lvs.py

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+import pya
+import sys
+
+layout = pya.Layout()
+layout.read("/tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/alu_w32_5ops.gds")
+
+top_cell = None
+for tc in layout.top_cells():
+    if tc.name == "alu_w32_5ops" or tc.name != "OUTLINE":
+        top_cell = tc
+        break
+
+if top_cell is None:
+    print("ERROR: No top cell found")
+    sys.exit(1)
+
+skip_patterns = ["sky130_fd_sc_hd__fill_", "sky130_fd_sc_hd__decap_", "sky130_fd_sc_hd__conb_"]
+
+removed = 0
+to_delete = []
+for inst in top_cell.each_inst():
+    cell_name = inst.cell.name
+    for pat in skip_patterns:
+        if pat in cell_name:
+            to_delete.append(inst)
+            break
+
+for inst in to_delete:
+    inst.delete()
+    removed += 1
+
+print("Removed %d non-logic cell instances" % removed)
+
+# Remove orphaned cell definitions
+used_cells = set()
+for cell in layout.each_cell():
+    for inst in cell.each_inst():
+        used_cells.add(inst.cell.cell_index())
+used_cells.add(top_cell.cell_index())
+
+orphans = []
+for cell in layout.each_cell():
+    if cell.cell_index() not in used_cells and cell.cell_index() != top_cell.cell_index():
+        orphans.append(cell.cell_index())
+
+for ci in orphans:
+    layout.delete_cell(ci)
+
+print("Removed %d orphaned cell definitions" % len(orphans))
+
+layout.write("/tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/lvs_cleaned.gds")
+print("Cleaned GDS written to /tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/lvs_cleaned.gds")

alu_w32_5ops_sky130_1000mhz/flow/design_only.cdl.gz

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:4d112279e2289317cf88540e4a86a031b8b347597483848d5d476b4fc43decfb
+size 5735

alu_w32_5ops_sky130_1000mhz/flow/drc_deck_patched.lydrc

@@ -0,0 +1,918 @@
+<?xml version="1.0" encoding="utf-8"?>
+<klayout-macro>
+ <description/>
+ <version/>
+ <category>drc</category>
+ <prolog/>
+ <epilog/>
+ <doc/>
+ <autorun>false</autorun>
+ <autorun-early>false</autorun-early>
+ <shortcut/>
+ <show-in-menu>true</show-in-menu>
+ <group-name>drc_scripts</group-name>
+ <menu-path>tools_menu.drc.end</menu-path>
+ <interpreter>dsl</interpreter>
+ <dsl-interpreter-name>drc-dsl-xml</dsl-interpreter-name>
+ <text>#
+#  DRC  for  SKY130 according to :
+#   https://skywater-pdk.readthedocs.io/en/latest/rules/periphery.html
+#   https://skywater-pdk.readthedocs.io/en/latest/rules/layers.html
+#
+#   Distributed under GNU GPLv3: https://www.gnu.org/licenses/
+#
+#  History :
+#   2020-10-04 : v1.0 : initial release
+#
+##########################################################################################
+
+# optionnal for a batch launch :   klayout -b -rd in_gds=my_layout.gds -rd report_file=6_drc_count.rpt -r drc_sky130.drc
+if $in_gds
+  source($in_gds, $topcell)
+end
+
+if $report_file
+  report("SKY130 DRC runset", $report_file)
+else
+  report("SKY130 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), "6_drc_count.rpt"))
+end
+
+AL = true  # do not change
+CU = false  # do not change
+# choose betwen only one of  AL  or  CU  back-end flow here :
+backend_flow = AL
+
+# enable / disable rule groups
+FEOL    = false # front-end-of-line checks
+BEOL    = true # back-end-of-line checks
+OFFGRID = true # manufacturing grid/angle checks
+
+# klayout setup
+########################
+# use a tile size of 1mm - not used in deep mode-
+tiles(1000.um)
+# use a tile border of 10 micron:
+tile_borders(1.um)
+#no_borders
+
+# hierachical
+deep
+
+# use 4 cpu cores
+threads(4)
+# if more inof is needed, set true
+verbose(true)
+
+# layers definitions
+########################
+
+# all except purpose (datatype) 5 -- label and 44 -- via
+li_wildcard = "67/0-4,6-43,45-*"
+mcon_wildcard = "67/44"
+
+m1_wildcard = "68/0-4,6-43,45-*"
+via_wildcard = "68/44"
+
+m2_wildcard = "69/0-4,6-43,45-*"
+via2_wildcard = "69/44"
+
+m3_wildcard = "70/0-4,6-43,45-*"
+via3_wildcard = "70/44"
+
+m4_wildcard = "71/0-4,6-43,45-*"
+via4_wildcard = "71/44"
+
+m5_wildcard = "72/0-4,6-43,45-*"
+
+diff = input(65, 20)
+tap = polygons(65, 44)
+nwell = polygons(64, 20)
+dnwell = polygons(64, 18)
+pwbm = polygons(19, 44)
+pwde = polygons(124, 20)
+natfet = polygons(124, 21)
+hvtr = polygons(18, 20)
+hvtp = polygons(78, 44)
+ldntm = polygons(11, 44)
+hvi = polygons(75, 20)
+tunm = polygons(80, 20)
+lvtn = polygons(125, 44)
+poly = polygons(66, 20)
+hvntm = polygons(125, 20)
+nsdm = polygons(93, 44)
+psdm = polygons(94, 20)
+rpm = polygons(86, 20)
+urpm = polygons(79, 20)
+npc = polygons(95, 20)
+licon = polygons(66, 44)
+
+li = polygons(li_wildcard)
+mcon = polygons(mcon_wildcard)
+
+m1 = polygons(m1_wildcard)
+via = polygons(via_wildcard)
+
+m2 = polygons(m2_wildcard)
+via2 = polygons(via2_wildcard)
+
+m3 = polygons(m3_wildcard)
+via3 = polygons(via3_wildcard)
+
+m4 = polygons(m4_wildcard)
+via4 = polygons(via4_wildcard)
+
+m5 = polygons(m5_wildcard)
+
+pad = polygons(76, 20)
+nsm = polygons(61, 20)
+capm = polygons(89, 44)
+cap2m = polygons(97, 44)
+vhvi = polygons(74, 21)
+uhvi = polygons(74, 22)
+npn = polygons(82, 20)
+inductor = polygons(82, 24)
+vpp = polygons(82, 64)
+pnp = polygons(82, 44)
+lvs_prune = polygons(84, 44)
+ncm = polygons(92, 44)
+padcenter = polygons(81, 20)
+mf = polygons(76, 44)
+areaid_sl = polygons(81, 1)
+areaid_ce = polygons(81, 2)
+areaid_fe = polygons(81, 3)
+areaid_sc = polygons(81, 4)
+areaid_sf = polygons(81, 6)
+areaid_sw = polygons(81, 7)
+areaid_sr = polygons(81, 8)
+areaid_mt = polygons(81, 10)
+areaid_dt = polygons(81, 11)
+areaid_ft = polygons(81, 12)
+areaid_ww = polygons(81, 13)
+areaid_ld = polygons(81, 14)
+areaid_ns = polygons(81, 15)
+areaid_ij = polygons(81, 17)
+areaid_zr = polygons(81, 18)
+areaid_ed = polygons(81, 19)
+areaid_de = polygons(81, 23)
+areaid_rd = polygons(81, 24)
+areaid_dn = polygons(81, 50)
+areaid_cr = polygons(81, 51)
+areaid_cd = polygons(81, 52)
+areaid_st = polygons(81, 53)
+areaid_op = polygons(81, 54)
+areaid_en = polygons(81, 57)
+areaid_en20 = polygons(81, 58)
+areaid_le = polygons(81, 60)
+areaid_hl = polygons(81, 63)
+areaid_sd = polygons(81, 70)
+areaid_po = polygons(81, 81)
+areaid_it = polygons(81, 84)
+areaid_et = polygons(81, 101)
+areaid_lvt = polygons(81, 108)
+areaid_re = polygons(81, 125)
+areaid_ag = polygons(81, 79)
+poly_rs = polygons(66, 13)
+diff_rs = polygons(65, 13)
+pwell_rs = polygons(64, 13)
+li_rs = polygons(67, 13)
+cfom = polygons(22, 20)
+
+
+# Define a new custom function that selects polygons by their number of holes:
+# It will return a new layer containing those polygons with min to max holes.
+# max can be nil to omit the upper limit.
+class DRC::DRCLayer
+  def with_holes(min, max)
+    new_data = RBA::Region::new
+    self.data.each do |p|
+      if p.holes &gt;= (min || 0) &amp;&amp; (!max || p.holes &lt;= max)
+        new_data.insert(p)
+      end
+    end
+    DRC::DRCLayer::new(@engine, new_data)
+  end
+end
+
+# DRC section
+########################
+info("DRC section")
+
+if FEOL
+info("FEOL section")
+gate = diff &amp; poly
+
+#   dnwell
+dnwell.width(3.0, euclidian).output("dnwell.2", "dnwell.2 : min. dnwell width : 3.0um")
+dnwell.not(uhvi).not(areaid_po).isolated(6.3, euclidian).output("dnwell.3", "dnwell.3 : min. dnwell spacing : 6.3um")
+dnwell.and(pnp).output("dnwell.4", "dnwell.4 : dnwell must not overlap pnp")
+dnwell.and(psdm).edges.not(psdm.edges).output("dnwell.5", "p+ must not straddle dnwell")
+# dnwell.6 rue not coded
+
+#   nwell
+nwell.width(0.84, euclidian).output("nwell.1", "nwell.1 : min. nwell width : 0.84um")
+nwell.isolated(1.27, euclidian).output("nwell.2a", "nwell.2a : min. nwell spacing (merged if less) : 1.27um")
+# rule nwell.4 is suitable for digital cells
+#nwell.not(uhvi).not(areaid_en20).not_interacting(tap.and(licon).and(li)).output("nwell.4", "nwell4 : all nwell exempt inside uhvi must contain a n+tap")
+nwell.enclosing(dnwell.not(uhvi).not(areaid_po), 0.4, euclidian).output("nwell.5", "nwell.5 : min. nwell enclosing dnwell exempt unside uhvi : 0.4um")
+dnwell.enclosing(nwell.not(uhvi), 1.03, euclidian).output("nwell.6", "nwell.6 : min. dnwell enclosing nwell exempt unside uhvi : 1.03um")
+dnwell.separation(nwell, 4.5, euclidian).output("nwell.7", "nwell.7 : min. dnwell separation nwell : 4.5um")
+
+#   pwbm
+pwbm.not(uhvi).output("pwbm", "pwbm must be inside uhvi")
+dnwell.and(uhvi).edges.not(pwbm).output("pwbm.4", "pwbm.4 : dnwell inside uhvi must be enclosed by pwbm")
+
+#   pwde
+pwde.not(pwbm).output("pwdem.3", "pwdem.3 : pwde must be inside pwbm")
+pwde.not(uhvi).output("pwdem.4", "pwdem.4 : pwde must be inside uhvi")
+pwde.not(dnwell).output("pwdem.5", "pwdem.5 : pwde must be inside dnwell")
+
+#   hvtp
+#hvtp.not(nwell).output("hvtp", "hvtp must inside nwell")
+hvtp.width(0.38, euclidian).output("hvtp.1", "hvtp.1 : min. hvtp width : 0.38um")
+hvtp.isolated(0.38, euclidian).output("hvtp.2", "hvtp.2 : min. hvtp spacing : 0.38um")
+hvtp.enclosing(gate.and(psdm), 0.18, euclidian).output("hvtp.3", "hvtp.3 : min. hvtp enclosure of pfet gate : 0.18um")
+hvtp.separation(gate.and(psdm), 0.18, euclidian).output("hvtp.4", "hvtp.4 : min. hvtp spacing pfet gate: 0.18um")
+hvtp.with_area(0..0.265).output("hvtp.5", "hvtp.5 : min. hvtp area : 0.265um²")
+
+#   hvtr
+hvtr.width(0.38, euclidian).output("hvtr.1", "hvtr.1 : min. hvtr width : 0.38um")
+hvtr.isolated(0.38, euclidian).output("hvtr.2", "hvtr.2 : min. hvtr spacing : 0.38um")
+
+#   lvtn
+lvtn.width(0.38, euclidian).output("lvtn.1", "lvtn.1 : min. lvtn width : 0.38um")
+lvtn.isolated(0.38, euclidian).output("lvtn.2", "lvtn.2 : min. lvtn spacing : 0.38um")
+lvtn.separation(diff.and(poly).not(uhvi), 0.18, euclidian).output("lvtn.3a", "lvtn.3a : min. lvtn spacing to gate : 0.18um")
+lvtn.separation(diff.and(nwell).not(poly), 0.235, projection).output("lvtn.3b", "lvtn.3b : min. lvtn spacing to pfet s/d : 0.18um")
+lvtn.enclosing(gate.not(uhvi), 0.18, euclidian).output("lvtn.4b", "lvtn.4b : min. lvtn enclosing to gate : 0.18um")
+lvtn.separation(hvtp, 0.38, euclidian).output("lvtn.9", "lvtn.9 : min. lvtn spacing hvtp : 0.38um")
+nwell.not_interacting(gate.and(nwell.not(hvi).not(areaid_ce))).enclosing(lvtn.not(uhvi), 0.18, euclidian).polygons.without_area(0).output("lvtn.4b", "lvtn.4b : min. lvtn enclosure of gate : 0.18um")
+lvtn.separation(nwell.inside(areaid_ce), 0.38, euclidian).output("lvtn.12", "lvtn.12 : min. lvtn spacing nwell inside areaid.ce : 0.38um")
+lvtn.with_area(0..0.265).output("lvtn.13", "lvtn.13 : min. lvtn area : 0.265um²")
+
+#   ncm
+ncm.and(tap.and(nwell).or(diff.not(nwell))).output("ncm.x.3", "ncm.x.3 : ncm must not overlap n+diff")
+ncm.width(0.38, euclidian).output("ncm.1", "ncm.1 : min. ncm width : 0.38um")
+ncm.isolated(0.38, euclidian).output("ncm.2", "ncm.2 : min. ncm spacing manual merge if smaller : 0.38um")
+ncm.enclosing(diff.and(nwell), 0.18, euclidian).output("ncm.3", "ncm.3 : min. ncm enclosure of p+diff : 0.18um")
+ncm.separation(lvtn.and(diff), 0.23, euclidian).output("ncm.5", "ncm.5 : min. ncm spacing lvtn diff : 0.23um")
+ncm.separation(diff.not(nwell), 0.2, euclidian).output("ncm.6", "ncm.6 : min. ncm spacing nfet : 0.2um")
+ncm.with_area(0..0.265).output("ncm.7", "ncm.13 : min. ncm area : 0.265um²")
+
+#   diff-tap
+difftap = diff + tap
+difftap.width(0.15, euclidian).output("difftap.1", "difftap.1 : min. difftap width : 0.15um")
+not_in_cell1 = layout(source.cell_obj).select("s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b" , "-s8fpls_pl8", "-s8fpls_rdrv4" , "-s8fpls_rdrv4f", "-s8fpls_rdrv8")
+not_in_cell1_diff = not_in_cell1.input(65, 20)
+not_in_cell1_diff.not(areaid_sc).not(poly).edges.and(gate.edges).with_length(0,0.42).output("difftap.2", "difftap.2: min. gate (exempt areaid.sc) width : 0.42um")
+diff.and(areaid_sc).not(poly).edges.and(gate.edges).with_length(0,0.36).output("difftap.2", "difftap.2: min. gate inside areaid.sc width : 0.36um")
+difftap.isolated(0.27, euclidian).output("difftap.3", "difftap.3 : min. difftap spacing : 0.27um")
+tap.edges.and(diff.edges).with_length(0,0.29).output("difftap.4", "difftap.4 : min. tap bound by diffusion : 0.29um")
+tap.edges.and(diff.edges).space(0.4, projection).output("difftap.5", "difftap.5 : min. tap bound by 2 diffusions : 0.4um")
+(tap.edges.and(diff.edges)).extended(0.01, 0.01, 0, 0, false).not(tap.and(diff)).and(diff.or(tap)).output("difftap.6", "difftap.6 : diff and tap not allowed to extend beyong their abutting ege")
+tap.edges.not_interacting(diff.edges).separation(diff.edges, 0.13, euclidian).output("difftap.7", "difftap.7 : min. diff/tap spacing to non-coincident diff edge : 0.13um")
+diff.edges.not_interacting(tap.edges).separation(tap.edges, 0.13, euclidian).output("difftap.7", "difftap.7 : min. diff/tap spacing to non-coincident tap edge : 0.13um")
+nwell.enclosing(diff.not(uhvi).and(psdm), 0.18, euclidian).output("difftap.8", "difftap.8 : min. p+diff enclosure by nwell : 0.18um")
+diff.not(uhvi).and(nsdm).separation(nwell, 0.34, euclidian).output("difftap.9", "difftap.9 : min. n+diff spacing to nwell : 0.34um")
+nwell.enclosing(tap.not(uhvi).and(nsdm), 0.18, euclidian).output("difftap.10", "difftap.10 : min. n+tap enclosure by nwell : 0.18um")
+tap.not(uhvi).and(psdm).separation(nwell, 0.13, euclidian).output("difftap.11", "difftap.11 : min. p+tap spacing to nwell : 0.13um")
+
+#   tunm
+tunm.width(0.41, euclidian).output("tunm.1", "tunm.1 : min. tunm width : 0.41um")
+tunm.isolated(0.5, euclidian).output("tunm.2", "tunm.2 : min. tunm spacing : 0.5um")
+tunm.enclosing(gate, 0.095, euclidian).output("tunm.3", "tunm.3 : min. tunm beyond gate : 0.095um")
+tunm.separation(gate.not_interacting(tunm), 0.095, euclidian).output("tunm.4", "tunm.4 : min. tunm spacing to gate outside tunm: 0.095um")
+gate.and(tunm).edges.not(gate.edges).output("tunm.5", "tunm.5 : gate must not straddle tunm")
+tunm.not(dnwell).output("tunm.6a", "tunm.6a : tunm not allowed outside dnwell")
+tunm.with_area(0..0.672).output("tunm.7", "tunm.7 : min. tunm area : 0.672um²")
+
+#   poly
+poly.width(0.15, euclidian).output("poly.1a", "poly.1a : min. poly width : 0.15um")
+poly.not(diff).edges.and(gate.and(lvtn).edges).space(0.35, euclidian).output("poly.1b", "poly.1b: min. lvtn gate width : 0.35um")
+poly.isolated(0.21, euclidian).output("poly.2", "poly.2 : min. poly spacing : 0.21um")
+poly.and(rpm.or(urpm).or(poly_rs)).width(0.33, euclidian).output("poly.3", "poly.3 : min. poly resistor width : 0.33um")
+poly.not(gate).separation(diff, 0.075, projection).polygons.without_area(0).output("poly.4", "poly.4 : min. poly on field spacing to diff : 0.075um")
+poly.not(gate).separation(tap, 0.055, euclidian).output("poly.5", "poly.5 : min. poly on field spacing to tap : 0.055um")
+gate.separation(tap, 0.3, projection).polygons.and(diff).output("poly.6", "poly.6 : min. gate spacing to tap : 0.3um")
+diff.enclosing(gate, 0.25, projection).polygons.without_area(0).output("poly.7", "poly.7 : min. source/drain length : 0.25um")
+poly.enclosing(gate, 0.13, projection).polygons.without_area(0).output("poly.8", "poly.8 : min. poly extention gate (endcap) : 0.13um")
+poly.and(rpm.or(urpm).or(poly_rs)).separation(poly.or(difftap), 0.48, euclidian).polygons.without_area(0).output("poly.9", "poly.9 : min. poly resistor space to poly or diff/tap : 0.48um")
+diff.merged.edges.end_segments(0.01).and(poly).output("poly.10", "poly.10 : poly must not overlap diff corner")
+gate.with_angle(0 .. 90).output("poly.11", "poly.11 : non 90 degree angle gate")
+not_in_cell3 = layout(source.cell_obj).select("s8fgvr_n_fg2")
+not_in_cell3_poly = not_in_cell3.input(66, 20)
+not_in_cell3_poly.not(hvi).not(nwell.not(hvi)).and(tap).output("poly.12", "poly.12 : poly must not overlap tap")
+poly.and(diff_rs).output("poly.15", "poly.15 : poly must not overlap diff resistor")
+
+#   rpm
+rpm.width(1.27, euclidian).output("rpm.1a", "rpm.1a : min. rpm width : 1.27um")
+rpm.isolated(0.84, euclidian).output("rpm.2", "rpm.2 : min. rpm spacing : 0.84um")
+rpm.enclosing(poly.and(poly_rs).and(psdm), 0.2, euclidian).output("rpm.3", "rpm.3 : min. rpm enclosure of poly resistor : 0.2um")
+psdm.enclosing(poly.and(poly_rs).and(rpm), 0.11, euclidian).output("rpm.4", "rpm.4 : min. psdm enclosure of poly resistor : 0.11um")
+npc.enclosing(poly.and(poly_rs).and(rpm), 0.095, euclidian).output("rpm.5", "rpm.5 : min. npc enclosure of poly resistor : 0.095um")
+rpm.separation(nsdm, 0.2, euclidian).output("rpm.6", "rpm.6 : min. rpm spacing nsdm: 0.2um")
+rpm.separation(poly, 0.2, euclidian).output("rpm.7", "rpm.7 : min. rpm spacing poly: 0.2um")
+rpm.and(poly).edges.not(poly.edges).output("rpm.8", "rpm.8 : poly must not straddle rpm")
+poly.and(poly_rs).and(rpm).separation(hvntm, 0.185, euclidian).output("rpm.9", "rpm.9 : min. poly resistor spacing hvntm: 0.185um")
+rpm.and(pwbm).output("rpm.10", "rpm.107 : min. rpm spacing pwbm: na")
+
+#   varac
+varac = poly &amp; tap &amp; (nwell - hvi) - areaid_ce
+tap.not(poly).edges.and(varac.edges).space(0.18, euclidian).output("varac.1", "varac.1: min. varac channel length : 0.18um")
+tap.and(poly).edges.and(varac.edges).space(1.0, euclidian).output("varac.2", "varac.2: min. varac channel wdth : 1.0um")
+varac.separation(hvtp, 0.18, euclidian).output("varac.3", "varac.3: min. varac channel space to hvtp : 0.18um")
+varac.separation(licon.and(tap), 0.25, euclidian).output("varac.4", "varac.4: min. varac channel space to licon on tap : 0.25um")
+nwell.enclosing(poly.overlapping(varac), 0.15, euclidian).output("varac.5", "varac.5: min. nwell enclosure of poly overlapping varac channel : 0.15um")
+tap.overlapping(varac).separation(difftap, 0.27, euclidian).polygons.without_area(0).output("varac.6", "varac.6: min. varac channel tap space to difftap : 0.27um")
+nwell.overlapping(varac).and(diff.and(nwell)).output("varac.7", "varac.7:  nwell overlapping varac channel must not overlap p+diff")
+
+#   photo
+photodiode = dnwell &amp; areaid_po
+photodiode.edges.without_length(3.0).output("photo.2", "photo.2 : minimum/maximum width of photodiode : 3.0um")
+photodiode.isolated(5.0, euclidian).output("photo.3", "photo.3 : mini. photodiode spacing : 5.0um")
+photodiode.separation(dnwell, 5.3, euclidian).output("photo.4", "photo.4 : mini. photodiode spacing to dnwell : 5.3um")
+areaid_po.not(dnwell).output("photo.5.6", "photo.5.6 : photodiode edges must coincide areaid.po and enclosed by dnwell")
+photodiode.not(tap.not(nwell).holes).output("photo.7", "photo.7 : photodiode must be enclosed by p+tap ring")
+photodiode.and(nwell).edges.without_length(0.84).output("photo.8", "photo.8 : minimum/maximum width of nwell inside photodiode : 0.84um")
+areaid_po.edges.and(photodiode.and(nwell).sized(1.08)).without_length(12.0).output("photo.9", "photo.9 : minimum/maximum enclosure of nwell by photodiode : 1.08um")
+photodiode.and(tap).edges.without_length(0.41).output("photo.10", "photo.10 : minimum/maximum width of tap inside photodiode : 0.41um")
+
+#   npc
+npc.width(0.27, euclidian).output("npc.1", "npc.1 : min. npc width : 0.27um")
+npc.isolated(0.27, euclidian).output("npc.2", "npc.2 : min. npc spacing, should be mnually merge if less : 0.27um")
+npc.separation(gate, 0.09, euclidian).output("npc.4", "npc.4 : min. npc spacing to gate : 0.09um")
+
+#   nsdm/psdm
+npsdm = nsdm + psdm
+nsdm.width(0.38, euclidian).output("nsdm.1", "nsdm.1 : min. nsdm width : 0.38um")
+psdm.width(0.38, euclidian).output("psdm.1", "psdm.1 : min. psdm width : 0.38um")
+nsdm.isolated(0.38, euclidian).output("n/psdm.1", "n/psdm.1 : min. nsdm spacing, should be mnually merge if less : 0.38um")
+psdm.isolated(0.38, euclidian).output("n/psdm.1", "n/psdm.1 : min. psdm spacing, should be mnually merge if less : 0.38um")
+npsdm.enclosing(diff, 0.125, euclidian).polygons.not(tap.sized(0.125)).output("n/psdm.5a", "n/psdm.5a : min. n/psdm enclosure diff except butting edge : 0.125um")
+npsdm.enclosing(tap, 0.125, euclidian).polygons.not(diff.sized(0.125)).output("n/psdm.5b", "n/psdm.5b : min. n/psdm enclosure tap except butting edge : 0.125um")
+tap.edges.and(diff.edges).not(npsdm).output("n/psdm.6", "n/psdm.6 : min. n/psdm enclosure of butting edge : 0.0um")
+nsdm.and(difftap).separation(psdm.and(difftap), 0.13, euclidian).polygons.without_area(0).output("n/psdm.7", "n/psdm.7 : min. nsdm diff spacing to psdm diff except butting edge : 0.13um")
+diff.and((nsdm.and(nwell)).or(psdm.not(nwell))).output("n/psdm.8", "n/psdm.8 : diff should be the opposite type of well/substrate underneath")
+tap.and((nsdm.not(nwell)).or(psdm.and(nwell))).output("n/psdm.8", "n/psdm.8 : tap should be the same type of well/substrate underneath")
+tap.and(diff).without_area(0).output("tap and diff", "tap and diff must not overlap")
+nsdm.with_area(0..0.265).output("n/psdm.10a", "n/psdm.10a : min. nsdm area : 0.265um²")
+psdm.with_area(0..0.265).output("n/psdm.10b", "n/psdm.10b : min. psdm area : 0.265um²")
+
+#   licon
+licon.not(poly.interacting(poly_rs).and(rpm)).edges.without_length(0.17).output("licon.1", "licon.1 : minimum/maximum width of licon : 0.17um")
+licon.and(poly.interacting(poly_rs).and(rpm)).not_interacting((licon.and(poly.interacting(poly_rs).and(rpm)).edges.with_length(0.19)).or(licon.and(poly.interacting(poly_rs).and(rpm)).edges.with_length(2.0))).output("licon.1b/c", "licon.1b/c : minimum/maximum width/length of licon inside poly resistor : 2.0/0.19um")
+licon.isolated(0.17, euclidian).output("licon.2", "licon.2 : min. licon spacing : 0.17um")
+licon.and(poly.interacting(poly_rs).and(rpm)).edges.with_length(0.19).space(0.35, euclidian).output("licon.2b", "licon.2b : min. licon 0.19um edge on resistor spacing : 0.35um")
+licon.interacting(licon.and(poly.interacting(poly_rs).and(rpm)).edges.with_length(2.0)).separation(licon.and(poly.interacting(poly_rs).and(rpm)), 0.51, euclidian).output("licon.2c", "licon.2c : min. licon 2.0um edge on resistor spacing : 0.51um")
+licon.and(poly.interacting(poly_rs).and(rpm)).separation(licon.not(poly.interacting(poly_rs).and(rpm)), 0.51, euclidian).output("licon.2d", "licon.2d : min. licon on resistor spacing other licon : 0.51um")
+# rule licon.3 not coded
+licon.not(li).not(poly.or(diff).or(tap)).output("licon.4", "licon.4 : min. licon must overlap li and (poly or tap or diff) ")
+diff.enclosing(licon, 0.04, euclidian).output("licon.5", "licon.5 : min. diff enclosure of licon : 0.04um")
+tap.edges.and(diff.edges).separation(licon.and(tap).edges, 0.06, euclidian).output("licon.6", "licon.6 : min. abutting edge spacing to licon tap : 0.06um")
+licon_edges_with_less_enclosure_tap = tap.enclosing(licon, 0.12, projection).second_edges
+opposite1 = (licon.edges - licon_edges_with_less_enclosure_tap).width(0.17 + 1.dbu, projection).polygons
+licon.not_interacting(opposite1).output("licon.7", "licon.7 : min. tap enclosure of licon by one of 2 opposite edges : 0.12um")
+poly.enclosing(licon, 0.05, euclidian).output("licon.8", "licon.8 : min. poly enclosure of licon : 0.05um")
+licon008 = licon.interacting(poly.enclosing(licon, 0.08, euclidian).polygons)
+licon_edges_with_less_enclosure_poly = poly.enclosing(licon, 0.08, projection).second_edges
+opposite2 = (licon.edges - licon_edges_with_less_enclosure_poly).width(0.17 + 1.dbu, projection).polygons
+licon008.not_interacting(opposite2).output("licon.8a", "licon.8a : min. poly enclosure of licon by one of 2 opposite edges : 0.08um")
+# rule licon.9 not coded
+licon.and(tap.and(nwell.not(hvi))).separation(varac, 0.25, euclidian).output("licon.10", "licon.10 : min. licon spacing to varac channel : 0.25um")
+not_in_cell4 = layout(source.cell_obj).select("-s8fs_gwdlvx4", "-s8fs_gwdlvx8", "-s8fs_hvrsw_x4", "-s8fs_hvrsw8", "-s8fs_hvrsw264", "-s8fs_hvrsw520", "-s8fs_rdecdrv", "-s8fs_rdec8”, “s8fs_rdec32", "-s8fs_rdec264", "-s8fs_rdec520")
+not_in_cell4_licon = not_in_cell4.input(66, 44)
+not_in_cell4_licon.and(diff.or(tap)).separation(gate.not(areaid_sc), 0.055, euclidian).output("licon.11", "licon.11 : min. licon spacing to gate : 0.055um")
+licon.and(diff.or(tap)).separation(gate.and(areaid_sc), 0.05, euclidian).output("licon.11a", "licon.11a : min. licon spacing to gate inside areaid.sc : 0.05um")
+in_cell4 = layout(source.cell_obj).select("+s8fs_gwdlvx4", "+s8fs_gwdlvx8", "+s8fs_hvrsw_x4", "+s8fs_hvrsw8", "+s8fs_hvrsw264", "+s8fs_hvrsw520")
+in_cell4_licon = in_cell4.input(66, 44)
+in_cell4_licon.and(diff.or(tap)).separation(gate, 0.04, euclidian).output("licon.11c", "licon.11c : min. licon spacing to gate for specific cells: 0.04um")
+# rules 11.b , 11.d not coded
+diff.interacting(gate).not(diff.interacting(gate).width(5.7, euclidian).polygons).output("licon.12", "licon.12 : max. sd width without licon : 5.7um")
+licon.and(diff.or(tap)).separation(npc, 0.09, euclidian).output("licon.13", "licon.13 : min. difftap licon spacing to npc : 0.09um")
+licon.and(poly).separation(diff.or(tap), 0.19, euclidian).output("licon.14", "licon.14 : min. poly licon spacing to difftap : 0.19um")
+npc.enclosing(licon.and(poly), 0.1, euclidian).output("licon.15", "licon.15 : min. npc enclosure of poly-licon : 0.1um")
+# rule licon.16 not applicable for the diff for the nmos of a nand gates or the pmos of a nor gates
+#diff.not(gate).not_interacting(licon).output("licon.16", "licon.16 : diff must enclose one licon")
+tap.not(uhvi).not_interacting(licon).output("licon.16", "licon.16 : tap must enclose one licon")
+poly.and(tap).edges.not(tap.edges).output("licon.17", "licon.17 : tap must not straddle poly")
+npc.not_interacting(licon.and(poly)).output("licon.18", "licon.18 : npc mut enclosed one poly-licon")
+
+#   vpp
+vpp.width(1.43, euclidian).output("vpp.1", "vpp.1 : min. vpp width : 1.43um")
+# rules 1.b, 1.c not coded
+vpp.and(poly.or(difftap)).output("vpp.3", "vpp.3 : vpp must not overlapp poly or diff or tap")
+vpp.and(nwell).edges.not(vpp.edges).output("vpp.4", "vpp.4 : vpp must not straddle nwell")
+vpp.and(dnwell).edges.not(vpp.edges).output("vpp.4", "vpp.4 : vpp must not straddle dnwell")
+vpp.and(poly.or(li).or(m1).or(m2)).separation(poly.or(li).or(m1).or(m2), 1.5, euclidian).polygons.with_area(2.25,nil).output("vpp.5", "vpp.5 : min. vpp spacing to poly or li or m1 or m2 : 1.5um")
+vpp.with_area(0..area(vpp.and(m3))*0.25).output("vpp.5a", "vpp.5a : max. m3 density in vpp : 0.25")
+vpp.with_area(0..area(vpp.and(m4))*0.3).output("vpp.5b", "vpp.5b : max. m4 density in vpp : 0.3")
+vpp.with_area(0..area(vpp.and(m5))*0.4).output("vpp.5c", "vpp.5c : max. m5 density in vpp : 0.4")
+nwell.enclosing(vpp, 1.5, euclidian).output("vpp.8", "vpp.8 : nwell enclosure of vpp : 1.5")
+vpp.separation(nwell, 1.5, euclidian).polygons.without_area(0).output("vpp.9", "vpp.9 : vpp spacing to nwell : 1.5")
+# rule vpp.10 not coded
+# rule vpp.11 not coded because moscap is not defined properly by any gds layer
+# rules vpp.12a, 12b, 12c not coded because specific to one cell
+if backend_flow = CU
+  m1.separation(vpp.and(m1), 0.16, euclidian).polygons.without_area(0).output("vpp.13", "vpp.13 : m1 spacing to m1inside vpp : 0.16")
+end
+
+# CAPM
+capm.width(1.0, euclidian).output("capm.1", "capm.1 : min. capm width : 1.0um")
+capm.isolated(0.84, euclidian).output("capm.2a", "capm.2a : min. capm spacing : 0.84um")
+m2.interacting(capm).isolated(1.2, euclidian).output("capm.2b", "capm.2b : min. capm spacing : 1.2um")
+m2.enclosing(capm, 0.14, euclidian).output("capm.3", "capm.3 : min. m2 enclosure of capm : 0.14um")
+capm.enclosing(via2, 0.14, euclidian).output("capm.4", "capm.4 : min. capm enclosure of via2 : 0.14um")
+capm.separation(via2, 0.14, euclidian).output("capm.5", "capm.5 : min. capm spacing to via2 : 0.14um")
+capm.sized(-20.0).sized(20.0).output("capm.6", "capm.6 : max. capm lenght/width : 20um")
+capm.with_angle(0 .. 90).output("capm.7", "capm.7 : capm not rectangle")
+capm.separation(via, 0.14, euclidian).polygons.without_area(0).output("capm.8", "capm.8 : min. capm spacing to via : 0.14um")
+capm.and(nwell).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle nwell")
+capm.and(diff).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle diff")
+capm.and(tap).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle tap")
+capm.and(poly).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle poly")
+capm.and(li).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle li")
+capm.and(m1).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle m1")
+capm.separation(m2.not_interacting(capm),  0.14, euclidian).output("capm.11", "capm.11 : min. capm spacing to m2 not overlapping capm : 0.5um")
+
+end #FEOL
+
+if BEOL
+info("BEOL section")
+
+#   li
+not_in_cell5 = source.select("-s8rf2_xcmvpp_hd5_*")
+not_in_cell5_li = not_in_cell5.polygons(li_wildcard)
+not_in_cell5_li.width(0.17, euclidian).output("li.1", "li.1 : min. li width : 0.17um")
+
+in_cell5_li = li - not_in_cell5_li
+in_cell5_li.width(0.14, euclidian).output("li.1a", "li.1a : min. li width for the cells s8rf2_xcmvpp_hd5_* : 0.14um")
+
+# rule li.2 not coded
+
+not_in_cell5_li.space(0.17, euclidian).output("li.3", "li.3 : min. li spacing : 0.17um")
+in_cell5_li.space(0.14, euclidian).output("li.3a", "li.3a : min. li spacing for the cells s8rf2_xcmvpp_hd5_* : 0.14um")
+licon08 = licon.interacting(li.enclosing(licon, 0.08, euclidian).polygons)
+licon_edges_with_less_enclosure_li = li.enclosing(licon, 0.08, projection).second_edges
+opposite3 = (licon.edges - licon_edges_with_less_enclosure_li).width(0.17 + 1.dbu, projection).polygons
+licon08.not_interacting(opposite3).output("li.5", "li.5 : min. li enclosure of licon of 2 opposite edges : 0.08um")
+li.with_area(0..0.0561).output("li.6", "li.6 : min. li area : 0.0561um²")
+
+#   ct
+mcon.edges.without_length(0.17).output("ct.1", "ct.1 : minimum/maximum width of mcon : 0.17um")
+mcon.space(0.19, euclidian).output("ct.2", "ct.2 : min. mcon spacing : 0.19um")
+# rule ct.3 not coded
+mcon.not(li).output("ct.4", "ct.4 : mcon should covered by li")
+if backend_flow = CU
+  li.interacting(li.and(m1).not(mcon).with_holes(1,10)).enclosing(mcon, 0.2, euclidian).output("ct.irdrop.1", "ct.irdrop.1 : min. li enclsoure of 1..10 mcon : 0.2um")
+  li.interacting(li.and(m1).not(mcon).with_holes(11,100)).enclosing(mcon, 0.3, euclidian).output("ct.irdrop.2", "ct.irdrop.2 : min. li enclsoure of 11..100 mcon : 0.3um")
+end
+
+#   m1
+m1.width(0.14, euclidian).output("m1.1", "m1.1 : min. m1 width : 0.14um")
+
+huge_m1 = m1.sized(-1.5).sized(1.5)
+non_huge_m1 = m1 - huge_m1
+
+non_huge_m1.space(0.14, euclidian).output("m1.2", "m1.2 : min. m1 spacing : 0.14um")
+
+(huge_m1.separation(non_huge_m1, 0.28, euclidian) + huge_m1.space(0.28, euclidian)).output("m1.3ab", "m1.3ab : min. 3um.m1 spacing m1 : 0.28um")
+
+not_in_cell6 = layout(source.cell_obj).select("-s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b", "-s8fpls_pl8", "-s8fs_cmux4_fm")
+not_in_cell6_m1 = not_in_cell6.input(m1_wildcard)
+not_in_cell6_m1.enclosing(mcon, 0.03, euclidian).output("m1.4", "m1.4 : min. m1 enclosure of mcon : 0.03um")
+in_cell6 = layout(source.cell_obj).select("+s8cell_ee_plus_sseln_a", "+s8cell_ee_plus_sseln_b", "+s8cell_ee_plus_sselp_a", "+s8cell_ee_plus_sselp_b", "+s8fpls_pl8", "+s8fs_cmux4_fm")
+in_cell6_m1 = in_cell6.input(m1_wildcard)
+in_cell6_m1.enclosing(mcon, 0.005, euclidian).output("m1.4a", "m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um")
+m1.with_area(0..0.083).output("m1.6", "m1.6 : min. m1 area : 0.083um²")
+m1.holes.with_area(0..0.14).output("m1.7", "m1.7 : min. m1 holes area : 0.14um²")
+if backend_flow = AL
+  mcon06 = mcon.interacting(poly.enclosing(m1, 0.06, euclidian).polygons)
+  mcon_edges_with_less_enclosure_m1 = m1.enclosing(mcon, 0.06, projection).second_edges
+  opposite4 = (mcon.edges - mcon_edges_with_less_enclosure_m1).width(0.17 + 1.dbu, projection).polygons
+  mcon06.not_interacting(opposite4).output("m1.5", "m1.5 : min. m1 enclosure of mcon of 2 opposite edges : 0.06um")
+  # rule m1.pd.1, rule m1.pd.2a, rule m1.pd.2b not coded
+end
+if bakend_flow = CU
+  m1.sized(-2.0).sized(2.0).output("m1.11", "m1.11 : max. m1 width after slotting : 4.0um")
+  # rule m1.12 not coded because inconsistent with m1.11
+  # rule m1.13, m1.14, m1.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759
+end
+
+#   via
+#rule via.3 not coded
+via.not(m1).output("via.4c.5c", "via.4c.5c : m1 must enclose all via")
+if backend_flow = AL
+  via.not(areaid_mt).edges.without_length(0.15).output("via.1a", "via.1a : minimum/maximum width of via : 0.15um")
+  via.and(areaid_mt).not_interacting((via.and(areaid_mt).edges.without_length(0.15)).or(via.and(areaid_mt).edges.without_length(0.23)).or(via.and(areaid_mt).edges.without_length(0.28))).output("via.1b", "via.1b : minimum/maximum width of via in areaid.mt: 0.15um or 0.23um or 0.28um")
+  via.isolated(0.17, euclidian).output("via.2", "via.2 : min. via spacing : 0.17um")
+  m1.enclosing(via.not_interacting(via.edges.without_length(0.15)), 0.055, euclidian).output("via.4a", "via.4a : min. m1 enclosure of 0.15um via : 0.055um")
+  m1.enclosing(via.not_interacting(via.edges.without_length(0.23)), 0.03, euclidian).output("via.4b", "via.4b : min. m1 enclosure of 0.23um via : 0.03um")
+  via1_edges_with_less_enclosure_m1 = m1.enclosing(via.not_interacting(via.edges.without_length(0.15)), 0.085, projection).second_edges
+  opposite5 = (via.not_interacting(via.edges.without_length(0.15)).edges - via1_edges_with_less_enclosure_m1).width(0.15 + 1.dbu, projection).polygons
+  via.not_interacting(via.edges.without_length(0.15)).not_interacting(opposite5).output("via1.5a", "via1.5a : min. m1 enclosure of 0.15um via of 2 opposite edges : 0.085um")
+  via2_edges_with_less_enclosure_m1 = m1.enclosing(via.not_interacting(via.edges.without_length(0.23)), 0.06, projection).second_edges
+  opposite6 = (via.not_interacting(via.edges.without_length(0.23)).edges - via2_edges_with_less_enclosure_m1).width(0.23 + 1.dbu, projection).polygons
+  via.not_interacting(via.edges.without_length(0.23)).not_interacting(opposite6).output("via1.5b", "via1.5b : min. m1 enclosure of 0.23um via of 2 opposite edges : 0.06um")
+end
+if backend_flow = CU
+  via.not(areaid_mt).edges.without_length(0.18).output("via.11", "via.11 : minimum/maximum width of via : 0.18um")
+  via.isolated(0.13, euclidian).output("via.12", "via.12 : min. via spacing : 0.13um")
+  # rule via.13 not coded because not understandable
+  via1_edges_with_less_enclosure_m1 = m1.enclosing(via, 0.04, projection).second_edges
+  opposite5 = (via.edges - via1_edges_with_less_enclosure_m1).width(0.18 + 1.dbu, projection).polygons
+  via.not_interacting(opposite5).output("via1.14", "via1.14 : min. m1 enclosure of 0.04um via of 2 opposite edges : 0.04um")
+  # rules via.irdrop.1, via.irdrop.2, via.irdrop.3, via.irdrop.4 not coded because not understandable
+end
+
+#   m2
+m2.width(0.14, euclidian).output("m2.1", "m2.1 : min. m2 width : 0.14um")
+
+huge_m2 = m2.sized(-1.5).sized(1.5)
+non_huge_m2 = m2 - huge_m2
+
+non_huge_m2.space(0.14, euclidian).output("m2.2", "m2.2 : min. m2 spacing : 0.14um")
+
+(huge_m2.separation(non_huge_m2, 0.28, euclidian) + huge_m2.space(0.28, euclidian)).output("m2.3ab", "m2.3ab : min. 3um.m2 spacing m2 : 0.28um")
+
+# rule m2.3c not coded
+m2.with_area(0..0.0676).output("m2.6", "m2.6 : min. m2 area : 0.0676um²")
+m2.holes.with_area(0..0.14).output("m2.7", "m2.7 : min. m2 holes area : 0.14um²")
+via.not(m2).output("m2.via", "m2.via : m2 must enclose via")
+if backend_flow = AL
+  m2.enclosing(via, 0.055, euclidian).output("m2.4", "m2.4 : min. m2 enclosure of via : 0.055um")
+  via_edges_with_less_enclosure_m2 = m2.enclosing(via, 0.085, projection).second_edges
+  opposite7 = (via.edges - via_edges_with_less_enclosure_m2).width(0.2 + 1.dbu, projection).polygons
+  via.not_interacting(opposite7).output("m2.5", "m2.5 : min. m2 enclosure of via of 2 opposite edges : 0.085um")
+  # rule m2.pd.1, rule m2.pd.2a, rule m2.pd.2b not coded
+end
+if bakend_flow = CU
+  m2.sized(-2.0).sized(2.0).output("m2.11", "m2.11 : max. m2 width after slotting : 4.0um")
+  # rule m2.12 not coded because inconsistent with m2.11
+  # rule m2.13, m2.14, m2.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759
+end
+
+#   via2
+#rule via233 not coded
+via2.not(m2).output("via2", "via2 : m2 must enclose all via2")
+if backend_flow = AL
+  via2.not(areaid_mt).edges.without_length(0.2).output("via2.1a", "via2.1a : minimum/maximum width of via2 : 0.2um")
+  via2.and(areaid_mt).not_interacting((via2.and(areaid_mt).edges.without_length(0.2)).or(via2.and(areaid_mt).edges.without_length(1.2)).or(via2.and(areaid_mt).edges.without_length(1.5))).output("via2.1b", "via2.1b : minimum/maximum width of via2 in areaid.mt: 0.2um or 1.2um or 1.5um")
+  via2.isolated(0.2, euclidian).output("via2.2", "via2.2 : min. via2 spacing : 0.2um")
+  m2.enclosing(via2, 0.04, euclidian).output("via2.4", "via2.4 : min. m2 enclosure of via2 : 0.04um")
+  m2.enclosing(via2.not_interacting(via2.edges.without_length(1.5)), 0.14, euclidian).output("via2.4a", "via2.4a : min. m2 enclosure of 1.5um via2 : 0.14um")
+  via2_edges_with_less_enclosure_m2 = m2.enclosing(via2, 0.085, projection).second_edges
+  opposite8 = (via2.edges - via2_edges_with_less_enclosure_m2).width(0.2 + 1.dbu, projection).polygons
+  via2.not_interacting(opposite8).output("via2.5", "via2.5 : min. m2 enclosure of via2 of 2 opposite edges : 0.085um")
+end
+if backend_flow = CU
+  via2.edges.without_length(0.21).output("via2.11", "via2.11 : minimum/maximum width of via2 : 0.21um")
+  via2.isolated(0.18, euclidian).output("via2.12", "via2.12 : min. via2 spacing : 0.18um")
+  # rule via2.13 not coded because not understandable, or not clear
+  m2.enclosing(via2, 0.035, euclidian).output("via2.14", "via2.14 : min. m2 enclosure of via2 : 0.035um")
+  # rules via2.irdrop.1, via2.irdrop.2, via2.irdrop.3, via2.irdrop.4 not coded because not understandable
+end
+
+#   m3
+m3.width(0.3, euclidian).output("m3.1", "m3.1 : min. m3 width : 0.3um")
+
+huge_m3 = m3.sized(-1.5).sized(1.5)
+non_huge_m3 = m3 - huge_m3
+
+non_huge_m3.space(0.3, euclidian).output("m3.2", "m3.2 : min. m3 spacing : 0.3um")
+
+(huge_m3.separation(non_huge_m3, 0.4, euclidian) + huge_m3.space(0.4, euclidian)).output("m3.3ab", "m3.3ab : min. 3um.m3 spacing m3 : 0.4um")
+
+# rule m3.3c not coded
+m3.with_area(0..0.24).output("m3.6", "m3.6 : min. m3 area : 0.24um²")
+via2.not(m3).output("m3.via2", "m3.via2 : m3 must enclose via2")
+if backend_flow = AL
+  m3.enclosing(via2, 0.065, euclidian).output("m3.4", "m3.4 : min. m3 enclosure of via2 : 0.065um")
+  via2_edges_with_less_enclosure_m3 = m3.enclosing(via2, 0.085, projection).second_edges
+  # m3.5 N/A
+  # opposite9 = (via2.edges - via2_edges_with_less_enclosure_m3).width(0.3 + 1.dbu, projection).polygons
+  # via2.not_interacting(opposite9).output("m3.5", "m3.5 : min. m3 enclosure of via2 of 2 opposite edges : 0.085um")
+  # rule m3.pd.1, rule m3.pd.2a, rule m3.pd.2b not coded
+end
+if bakend_flow = CU
+  m3.holes.with_area(0..0.2).output("m3.7", "m3.7 : min. m3 holes area : 0.2um²")
+  m3.sized(-2.0).sized(2.0).output("m3.11", "m3.11 : max. m3 width after slotting : 4.0um")
+  # rule m3.12 not coded because inconsistent with m3.11
+  # rule m3.13, m3.14, m3.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759
+end
+
+#   via3
+#rule via3.3 not coded
+via3.not(m3).output("via3", "via3 : m3 must enclose all via3")
+if backend_flow = AL
+  via3.not(areaid_mt).edges.without_length(0.2).output("via3.1a", "via3.1a : minimum/maximum width of via3 : 0.2um")
+  via3.and(areaid_mt).not_interacting((via3.and(areaid_mt).edges.without_length(0.2)).or(via3.and(areaid_mt).edges.without_length(0.8))).output("via3.1a", "via3.1a : minimum/maximum width of via3 in areaid.mt: 0.2um or 0.8um")
+  via3.isolated(0.2, euclidian).output("via3.2", "via3.2 : min. via3 spacing : 0.2um")
+  m3.enclosing(via3, 0.06, euclidian).output("via3.4", "via3.4 : min. m3 enclosure of via3 : 0.06um")
+  via3_edges_with_less_enclosure_m3 = m3.enclosing(via3, 0.09, projection).second_edges
+  opposite10 = (via3.edges - via3_edges_with_less_enclosure_m3).width(0.2 + 1.dbu, projection).polygons
+  via3.not_interacting(opposite10).output("via3.5", "via3.5 : min. m2 enclosure of via3 of 2 opposite edges : 0.09um")
+end
+if backend_flow = CU
+  via3.edges.without_length(0.21).output("via3.11", "via3.11 : minimum/maximum width of via3 : 0.21um")
+  via3.isolated(0.18, euclidian).output("via3.12", "via3.12 : min. via3 spacing : 0.18um")
+  m3.enclosing(via3, 0.055, euclidian).output("via3.13", "via3.13 : min. m3 enclosure of via3 : 0.055um")
+  # rule via3.14 not coded because not understandable, or not clear
+  # rules via3.irdrop.1, via3.irdrop.2, via3.irdrop.3, via3.irdrop.4 not coded because not understandable
+end
+
+#   m4
+m4.width(0.3, euclidian).output("m4.1", "m4.1 : min. m4 width : 0.3um")
+
+huge_m4 = m4.sized(-1.5).sized(1.5)
+non_huge_m4 = m4 - huge_m4
+
+non_huge_m4.space(0.3, euclidian).output("m4.2", "m4.2 : min. m4 spacing : 0.3um")
+
+(huge_m4.separation(non_huge_m4, 0.4, euclidian) + huge_m4.space(0.4, euclidian)).output("m4.5ab", "m4.5ab : min. 3um.m4 spacing m4 : 0.4um")
+
+m4.with_area(0..0.24).output("m4.4", "m4.4 : min. m4 area : 0.24um²")
+via3.not(m4).output("m4.via3", "m4.via3 : m4 must enclose via3")
+if backend_flow = AL
+  m4.enclosing(via3, 0.065, euclidian).output("m4.3", "m4.3 : min. m4 enclosure of via3 : 0.065um")
+  # m4.5 doesn't exist
+  # via3_edges_with_less_enclosure_m4 = m4.enclosing(via2, 0.085, projection).second_edges
+  # opposite9 = (via3.edges - via3_edges_with_less_enclosure_m4).width(0.3 + 1.dbu, projection).polygons
+  # via3.not_interacting(opposite9).output("m4.5", "m4.5 : min. m4 enclosure of via3 of 2 opposite edges : 0.085um")
+  # rule m4.pd.1, rule m4.pd.2a, rule m4.pd.2b not coded
+end
+if bakend_flow = CU
+  m4.holes.with_area(0..0.2).output("m4.7", "m4.7 : min. m4 holes area : 0.2um²")
+  m4.sized(-5.0).sized(5.0).output("m4.11", "m4.11 : max. m4 width after slotting : 10.0um")
+  # rule m4.12 not coded because inconsistent with m4.11
+  # rule m4.13, m4.14, m4.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759
+  m4.enclosing(via3, 0.06, euclidian).output("m4.15", "m4.15 : min. m4 enclosure of via3 : 0.06um")
+end
+
+#   via4
+via4.edges.without_length(0.8).output("via4.1a", "via4.1a : minimum/maximum width of via4 : 0.8um")
+via4.isolated(0.8, euclidian).output("via4.2", "via4.2 : min. via4 spacing : 0.8um")
+#rule via4.3 not coded
+m4.enclosing(via4, 0.19, euclidian).output("via4.4", "via4.4 : min. m4 enclosure of via4 : 0.19um")
+via4.not(m4).output("via4", "via4 : m4 must enclose all via4")
+if backend_flow = CU
+  # rules via4.irdrop.1, via4.irdrop.2, via4.irdrop.3, via4.irdrop.4 not coded because not understandable
+end
+
+#   m5
+m5.width(1.6, euclidian).output("m5.1", "m5.1 : min. m5 width : 1.6um")
+
+m5.space(1.6, euclidian).output("m5.2", "m5.2 : min. m5 spacing : 1.6um")
+
+via4.not(m5).output("m5.via4", "m5.via4 : m5 must enclose via4")
+m5.enclosing(via4, 0.31, euclidian).output("m5.3", "m4.3 : min. m5 enclosure of via4 : 0.31um")
+
+#   nsm
+nsm.width(3.0, euclidian).output("nsm.1", "nsm.1 : min. nsm width : 3.0um")
+nsm.isolated(4.0, euclidian).output("nsm.2", "nsm.2 : min. nsm spacing : 4.0um")
+nsm.enclosing(diff, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of diff : 3.0um")
+nsm.enclosing(tap, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of tap : 3.0um")
+nsm.enclosing(poly, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of poly : 3.0um")
+nsm.enclosing(li, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of li : 3.0um")
+nsm.enclosing(m1, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m1 : 3.0um")
+nsm.enclosing(m2, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m2 : 3.0um")
+nsm.enclosing(m3, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m3 : 3.0um")
+nsm.enclosing(m4, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m4 : 3.0um")
+nsm.enclosing(m5, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m5 : 3.0um")
+nsm.enclosing(cfom, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of cfom : 3.0um")
+if backend_flow = AL
+  nsm.separation(diff, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to diff : 1.0um")
+  nsm.separation(tap, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to tap : 1.0um")
+  nsm.separation(poly, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to poly : 1.0um")
+  nsm.separation(li, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to li : 1.0um")
+  nsm.separation(m1, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m1 : 1.0um")
+  nsm.separation(m2, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m2 : 1.0um")
+  nsm.separation(m3, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m3 : 1.0um")
+  nsm.separation(m4, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m4 : 1.0um")
+  nsm.separation(m5, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m5 : 1.0um")
+  nsm.separation(cfom, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to cfom : 1.0um")
+end
+
+#   pad
+pad.isolated(1.27, euclidian).output("pad.2", "pad.2 : min. pad spacing : 1.27um")
+
+end #BEOL
+
+if FEOL
+info("FEOL section")
+
+#   mf
+mf.not_interacting(mf.edges.without_length(0.8)).output("mf.1", "mf.1 : minimum/maximum width of fuse : 0.8um")
+mf.not_interacting(mf.edges.without_length(7.2)).output("mf.2", "mf.2 : minimum/maximum length of fuse : 7.2um")
+mf.isolated(1.96, euclidian).output("mf.3", "mf.3 : min. fuse center spacing : 2.76um")
+# fuses need more clarification on fuse_shield, fuse layers ...
+
+#   hvi
+hvi.width(0.6, euclidian).output("hvi.1", "hvi.1 : min. hvi width : 0.6um")
+hvi.isolated(0.7, euclidian).output("hvi.2", "hvi.2 : min. hvi spacing, merge if less : 0.7um")
+hvi.and(tunm).output("hvi.4", "hvi.4 : hvi must not overlapp tunm")
+hvi.and(nwell).separation(nwell, 2.0, euclidian).output("hvnwell.8", "hvnwelli.8 : min. hvnwel spacing to nwell : 2.0")
+areaid_hl.not(hvi).output("hvnwel.9", "hvnwell.9 : hvi must overlapp hvnwell")
+# rule hvnell.10 not coded
+diff.not(psdm.and(diff_rs)).and(hvi).width(0.29, euclidian).output("hvdifftap.14", "hvdifftap.14 : min. diff inside hvi width : 0.29um")
+diff.and(psdm.and(diff_rs)).and(hvi).width(0.15, euclidian).output("hvdifftap.14a", "hvdifftap.14a : min. p+diff resistor inside hvi width : 0.15um")
+diff.and(hvi).isolated(0.3, euclidian).output("hvdifftap.15a", "hvdifftap.15a : min. diff inside hvi spacing : 0.3um")
+diff.and(hvi).and(nsdm).separation(diff.and(hvi).and(psdm), 0.37, euclidian).polygons.without_area(0).output("hvdifftap.15b", "hvdifftap.15b : min. n+diff inside hvi spacing to p+diff inside hvi except abutting: 0.37um")
+tap.and(hvi).edges.and(diff).without_length(0.7).output("hvdifftap.16", "hvdifftap.16 : min. tap inside hvi abuttng diff : 0.7um")
+hvi.and(nwell).enclosing(diff, 0.33, euclidian).output("hvdifftap.17", "hvdifftap.17 : min. hvnwell enclosure of p+diff : 0.33um")
+hvi.and(nwell).separation(diff, 0.43, euclidian).output("hvdifftap.18", "hvdifftap.18 : min. hvnwell spacing to n+diff : 0.43um")
+hvi.and(nwell).enclosing(tap, 0.33, euclidian).output("hvdifftap.19", "hvdifftap.19 : min. hvnwell enclosure of n+tap : 0.33um")
+hvi.and(nwell).separation(tap, 0.43, euclidian).output("hvdifftap.20", "hvdifftap.20 : min. hvnwell spacing to p+tap : 0.43um")
+hvi.and(diff).edges.not(diff.edges).output("hvdifftap.21", "hvdifftap.21 : diff must not straddle hvi")
+hvi.and(tap).edges.not(tap.edges).output("hvdifftap.21", "hvdifftap.21 : tap must not straddle hvi")
+hvi.enclosing(difftap, 0.18, euclidian).output("hvdifftap.22", "hvdifftap.22 : min. hvi enclosure of diff or tap : 0.18um")
+hvi.separation(difftap, 0.18, euclidian).output("hvdifftap.23", "hvdifftap.23 : min. hvi spacing to diff or tap : 0.18um")
+hvi.and(diff).not(nwell).separation(nwell, 0.43, euclidian).output("hvdifftap.24", "hvdifftap.24 : min. hv n+diff spacing to nwell : 0.43um")
+diff.and(hvi).not(nwell).isolated(1.07, euclidian).polygons.and(tap).output("hvdifftap.25", "hvdifftap.25 : min. n+diff inside hvi spacing accros p+tap  : 1.07um")
+diff.not(poly).edges.and(gate.and(hvi).edges).space(0.35, euclidian).output("hvpoly.13", "hvpoly.13: min. hvi gate length : 0.5um")
+hvi.and(poly).edges.not(poly.edges).output("hvpoly.14", "hvpoly.14 : poly must not straddle hvi")
+
+#   hvntm
+hvntm.width(0.7, euclidian).output("hvntm.1", "hvntm.1 : min. hvntm width : 0.7um")
+hvntm.isolated(0.7, euclidian).output("hvntm.2", "hvntm.2 : min. hvntm spacing : 0.7um")
+hvntm.enclosing(diff.and(nwell).and(hvi), 0.185, euclidian).output("hvntm.3", "hvntm.3 : min. hvntm enclosure of hv n+diff : 0.185um")
+hvntm.separation(diff.not(nwell).not(hvi), 0.185, euclidian).output("hvntm.4", "hvntm.4 : min. hvntm spacing to n+diff : 0.185um")
+hvntm.separation(diff.and(nwell).not(hvi), 0.185, euclidian).output("hvntm.5", "hvntm.5 : min. hvntm spacing to p+diff : 0.185um")
+hvntm.separation(tap.not(nwell).not(hvi), 0.185, euclidian).polygons.without_area(0).output("hvntm.6a", "hvntm.6a : min. hvntm spacing to p+tap : 0.185um")
+hvntm.and(areaid_ce).output("hvntm.9", "hvntm.9 : hvntm must not overlapp areaid.ce")
+
+#   denmos
+poly.not_interacting(pwde).interacting(areaid_en).width(1.055, projection).output("denmos.1", "denmos.1 : min. de_nfet gate width : 1.055um")
+diff.not_interacting(pwde).enclosing(poly.interacting(areaid_en), 0.28, projection).polygons.without_area(0).output("denmos.2", "denmos.2 : min. de_nfet source ouside poly width : 0.28um")
+diff.not_interacting(pwde).and(poly.interacting(areaid_en)).width(0.925, projection).output("denmos.3", "denmos.3 : min. de_nfet source inside poly width : 0.925um")
+diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).width(0.17, euclidian).output("denmos.4", "denmos.4 : min. de_nfet drain width : 0.17um")
+nwell.not_interacting(pwde).and(poly.interacting(areaid_en)).width(0.225, projection).polygons.or(nwell.and(poly.interacting(areaid_en)).sized(-0.1125).sized(0.1125)).output("denmos.5", "denmos.5 : min. de_nfet source inside nwell width : 0.225m")
+diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).separation(diff.interacting(poly.interacting(areaid_en)), 1.585, projection).output("denmos.6", "denmos.6 : min. de_nfet source spacing to drain : 1.585um")
+nwell.not_interacting(pwde).and(poly.and(diff).interacting(areaid_en)).edges.without_length(5.0, nil).output("denmos.7", "denmos.7 : min. de_nfet channel width : 5.0um")
+diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("denmos.8", "denmos.8 : 90deg. not allowed for de_nfet drain")
+nwell.not_interacting(pwde).interacting(areaid_en).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("denmos.9a", "denmos.9a : 90deg. not allowed for de_nfet nwell")
+nwell.not_interacting(pwde).interacting(areaid_en).edges.with_angle(45).without_length(0.607..0.609).output("denmos.9a", "denmos.9a : 45deg. bevels of de_nfet nwell should be 0.43um from corners")
+nwell.not_interacting(pwde).interacting(areaid_en).edges.with_angle(135).without_length(0.607..0.609).output("denmos.9a", "denmos.9a : 45deg. bevels of de_nfet nwell should be 0.43um from corners")
+diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(45).without_length(0.7..0.71).output("denmos.9b", "denmos.9b : 45deg. bevels of de_nfet drain should be 0.05um from corners")
+diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(135).without_length(0.7..0.71).output("denmos.9b", "denmos.9b : 45deg. bevels of de_nfet drain should be 0.05um from corners")
+nwell.not_interacting(pwde).enclosing(diff.interacting(areaid_en).not_interacting(poly), 0.66, euclidian).output("denmos.10", "denmos.10 : min. nwell enclosure of de_nfet drain : 0.66um")
+nwell.not_interacting(pwde).interacting(areaid_en).separation(tap.not(nwell), 0.86, euclidian).output("denmos.11", "denmos.11 : min. de_nfet nwell spacing to tap : 0.86um")
+nwell.not_interacting(pwde).interacting(areaid_en).isolated(2.4, euclidian).output("denmos.12", "denmos.12 : min. de_nfet nwell : 2.4um")
+nsdm.not_interacting(pwde).enclosing(diff.interacting(areaid_en).interacting(poly), 0.13, euclidian).output("denmos.13", "denmos.13 : min. nsdm enclosure of de_nfet source : 0.13um")
+
+#   depmos
+poly.interacting(pwde).interacting(areaid_en).width(1.05, projection).output("depmos.1", "depmos.1 : min. de_pfet gate width : 1.05um")
+diff.interacting(pwde).enclosing(poly.interacting(areaid_en), 0.28, projection).polygons.without_area(0).output("depmos.2", "depmos.2 : min. de_pfet source ouside poly width : 0.28um")
+diff.interacting(pwde).and(poly.interacting(areaid_en)).width(0.92, projection).output("depmos.3", "depmos.3 : min. de_pfet source inside poly width : 0.92um")
+diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).width(0.17, euclidian).output("depmos.4", "depmos.4 : min. de_pfet drain width : 0.17um")
+pwde.not(nwell).and(poly.interacting(areaid_en)).width(0.26, projection).polygons.or(pwde.not(nwell).and(poly.interacting(areaid_en)).sized(-0.13).sized(0.13)).output("depmos.5", "depmos.5 : min. de_pfet source inside nwell width : 0.26m")
+diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).separation(diff.interacting(poly.interacting(areaid_en)), 1.19, projection).output("depmos.6", "depmos.6 : min. de_pfet source spacing to drain : 1.19um")
+nwell.interacting(pwde).and(poly.and(diff).interacting(areaid_en)).edges.without_length(5.0, nil).output("depmos.7", "depmos.7 : min. de_pfet channel width : 5.0um")
+diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("depmos.8", "depmos.8 : 90deg. not allowed for de_pfet drain")
+pwde.not(nwell).interacting(areaid_en).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("depmos.9a", "depmos.9a : 90deg. not allowed for de_pfet pwell")
+pwde.not(nwell).interacting(areaid_en).edges.with_angle(45).without_length(0.607..0.609).output("depmos.9a", "depmos.9a : 45deg. bevels of de_pfet pwell should be 0.43um from corners")
+pwde.not(nwell).interacting(areaid_en).edges.with_angle(135).without_length(0.607..0.609).output("depmos.9a", "depmos.9a : 45deg. bevels of de_pfet pwell should be 0.43um from corners")
+diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(45).without_length(0.7..0.71).output("depmos.9b", "depmos.9b : 45deg. bevels of de_pfet drain should be 0.05um from corners")
+diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(135).without_length(0.7..0.71).output("depmos.9b", "depmos.9b : 45deg. bevels of de_pfet drain should be 0.05um from corners")
+nwell.interacting(pwde).separation(diff.interacting(areaid_en).not_interacting(poly), 0.86, euclidian).output("depmos.10", "depmos.10 : min. pwell enclosure of de_pfet drain : 0.86um")
+pwde.not(nwell).interacting(areaid_en).separation(tap.and(nwell), 0.66, euclidian).output("depmos.11", "depmos.11 : min. de_pfet pwell spacing to tap : 0.66um")
+psdm.interacting(pwde).enclosing(diff.interacting(areaid_en).interacting(poly), 0.13, euclidian).output("depmos.12", "depmos.12 : min. psdm enclosure of de_pfet source : 0.13um")
+
+#   extd
+areaid_en.and(difftap).edges.not(difftap.edges).output("extd.1", "extd.1 : difftap must not straddle areaid.en")
+difftap.interacting(areaid_en).not(poly).with_area(0).output("extd.2", "extd.2 : poly must not overlapp entirely difftap in areaid.en")
+# rules extd.4, extd.5, extd.6, extd.7 not coded because specific to some cells
+
+#   vhvi
+# rules vhvi.vhv.1, vhvi.vhv.2, vhvi.vhv.3, vhvi.vhv.4, vhvi.vhv.5, vhvi.vhv.6 not coded
+vhvi.width(0.02, euclidian).output("vhvi.1", "vhvi.1 : min. vhvi width : 0.02um")
+vhvi.and(areaid_ce).output("vhvi.2", "vhvi.2 : vhvi must not overlap areaid.ce")
+vhvi.and(hvi).output("vhvi.3", "vhvi.3 : vhvi must not overlap hvi")
+# rules vhvi.4, vhvi.6 not coded
+vhvi.and(diff).edges.not(diff.edges).output("vhvi.5", "vhvi.5 : vhvi must not straddle diff")
+vhvi.and(tap).edges.not(tap.edges).output("vhvi.5", "vhvi.5 : vhvi must not straddle tap")
+vhvi.and(poly).edges.not(poly.edges).output("vhvi.7", "vhvi.7 : vhvi must not straddle poly")
+
+nwell.and(vhvi).separation(nwell, 2.5, euclidian).output("hv.nwell.1", "hv.nwell.1 : min. vhvi nwell spacing to nwell : 2.5um")
+diff.and(vhvi).isolated(0.3, euclidian).output("hv.diff.1", "hv.diff.1 : min. vhvi diff spacing : 0.3um")
+nwell.interacting(diff.and(vhvi)).separation(diff.not(nwell), 0.43, euclidian).output("hv.diff.2", "hv.diff.2 : min. vhvi nwell spacing n+diff : 0.43um")
+diff.and(vhvi).not(nwell).separation(nwell, 0.55, euclidian).output("hv.diff.3a", "hv.diff.3a : min. vhvi n+diff spacing nwell : 0.55um")
+# rule hv.diff.3b not coded
+poly.and(vhvi).not(diff).separation(diff, 0.3, euclidian).polygons.without_area(0).output("hv.poly.2", "hv.poly.2 : min. vhvi poly spacing to diff : 0.3um")
+poly.and(vhvi).not(diff).separation(nwell, 0.55, euclidian).polygons.without_area(0).output("hv.poly.3", "hv.poly.3 : min. vhvi poly spacing to nwell : 0.55um")
+nwell.enclosing(poly.and(vhvi).not(diff), 0.3, euclidian).polygons.without_area(0).output("hv.poly.4", "hv.poly.4 : min. nwell enclosure of vhvi poly : 0.3um")
+#poly.and(vhvi).enclosing(diff.interacting(areaid_en), 0.16, projection).polygons.without_area(0).output("hv.poly.6", "hv.poly.6 : min. poly enclosure of hvfet gate : 0.16um")
+# rule hv.poly.7 not coded
+
+#   uhvi
+uhvi.and(diff).edges.not(diff.edges).output("uhvi.1", "uhvi.1 : diff must not straddle uhvi")
+uhvi.and(tap).edges.not(tap.edges).output("uhvi.1", "uhvi.1 : tap must not straddle uhvi")
+uhvi.and(poly).edges.not(poly.edges).output("uhvi.2", "uhvi.2 : poly must not straddle uhvi")
+pwbm.not(uhvi).output("uhvi.3", "uhvi.3 : uhvi must not enclose pwbm")
+uhvi.and(dnwell).edges.not(dnwell.edges).output("uhvi.4", "uhvi.4 : dnwell must not straddle uhvi")
+areaid_en20.not(uhvi).output("uhvi.5", "uhvi.5 : uhvi must not enclose areaid.en20")
+#dnwell.not(uhvi).output("uhvi.6", "uhvi.6 : uhvi must not enclose dnwell")
+natfet.not(uhvi).output("uhvi.7", "uhvi.7 : uhvi must not enclose natfet")
+
+#   pwell_res
+pwell_rs.width(2.65).output("pwres.2", "pwres.2 : min. pwell resistor width : 2.65um")
+pwell_rs.sized(-2.65).sized(2.65).output("pwres.2", "pwres.2 : max. pwell resistor width : 2.65um")
+pwell_rs.interacting(pwell_rs.edges.with_length(2.651,26.499)).output("pwres.3", "pwres.3 : min. pwell resistor length : 26.5um")
+pwell_rs.interacting(pwell_rs.edges.with_length(265.0, nil)).output("pwres.4", "pwres.4 : max. pwell resistor length : 265um")
+tap.interacting(pwell_rs).separation(nwell, 0.22, euclidian).output("pwres.5", "pwres.5 : min. pwell resistor tap spacing to nwell : 0.22um")
+tap.interacting(pwell_rs).and(tap.sized(0.22).and(nwell)).output("pwres.5", "pwres.5 : max. pwell resistor tap spacing to nwell : 0.22um")
+tap.interacting(pwell_rs).width(0.53).output("pwres.6", "pwres.6 : min. width of tap inside pwell resistor : 0.53um")
+tap.interacting(pwell_rs).sized(-0.265).sized(0.265).output("pwres.6", "pwres.6 : max. width of tap inside pwell resistor : 0.53um")
+# rules pwres.7a, pwres.7b not coded
+pwell_rs.and(diff).output("pwres.8", "pwres.8 : diff not allowed inside pwell resistor")
+pwell_rs.and(poly).output("pwres.8", "pwres.8 : poly not allowed inside pwell resistor")
+# rules pwres.9, pwres.10 not coded
+
+#   rf_diode
+areaid_re.with_angle(0 .. 90).output("rfdiode.1", "rfdiode.1 : non 90 degree angle areaid.re")
+areaid_re.not(nwell).or(nwell.interacting(areaid_re).not(areaid_re)).output("rfdiode.2", "rfdiode.2 : areaid.re must coincide rf nwell diode")
+# rule rfdiode.3 not coded
+
+end #FEOL
+
+if OFFGRID
+info("OFFGRID-ANGLES section")
+
+dnwell.ongrid(0.005).output("dnwell_OFFGRID", "x.1b : OFFGRID vertex on dnwell")
+dnwell.with_angle(0 .. 45).output("dnwell_angle", "x.3a : non 45 degree angle dnwell")
+nwell.ongrid(0.005).output("nwell_OFFGRID", "x.1b : OFFGRID vertex on nwell")
+nwell.with_angle(0 .. 45).output("nwell_angle", "x.3a : non 45 degree angle nwell")
+pwbm.ongrid(0.005).output("pwbm_OFFGRID", "x.1b : OFFGRID vertex on pwbm")
+pwbm.with_angle(0 .. 45).output("pwbm_angle", "x.3a : non 45 degree angle pwbm")
+pwde.ongrid(0.005).output("pwde_OFFGRID", "x.1b : OFFGRID vertex on pwde")
+pwde.with_angle(0 .. 45).output("pwde_angle", "x.3a : non 45 degree angle pwde")
+hvtp.ongrid(0.005).output("hvtp_OFFGRID", "x.1b : OFFGRID vertex on hvtp")
+hvtp.with_angle(0 .. 45).output("hvtp_angle", "x.3a : non 45 degree angle hvtp")
+hvtr.ongrid(0.005).output("hvtr_OFFGRID", "x.1b : OFFGRID vertex on hvtr")
+hvtr.with_angle(0 .. 45).output("hvtr_angle", "x.3a : non 45 degree angle hvtr")
+lvtn.ongrid(0.005).output("lvtn_OFFGRID", "x.1b : OFFGRID vertex on lvtn")
+lvtn.with_angle(0 .. 45).output("lvtn_angle", "x.3a : non 45 degree angle lvtn")
+ncm.ongrid(0.005).output("ncm_OFFGRID", "x.1b : OFFGRID vertex on ncm")
+ncm.with_angle(0 .. 45).output("ncm_angle", "x.3a : non 45 degree angle ncm")
+diff.ongrid(0.005).output("diff_OFFGRID", "x.1b : OFFGRID vertex on diff")
+tap.ongrid(0.005).output("tap_OFFGRID", "x.1b : OFFGRID vertex on tap")
+diff.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("diff_angle", "x.2 : non 90 degree angle diff")
+diff.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("diff_angle", "x.2c : non 45 degree angle diff")
+tap.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("tap_angle", "x.2 : non 90 degree angle tap")
+tap.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("tap_angle", "x.2c : non 45 degree angle tap")
+tunm.ongrid(0.005).output("tunm_OFFGRID", "x.1b : OFFGRID vertex on tunm")
+tunm.with_angle(0 .. 45).output("tunm_angle", "x.3a : non 45 degree angle tunm")
+poly.ongrid(0.005).output("poly_OFFGRID", "x.1b : OFFGRID vertex on poly")
+poly.with_angle(0 .. 90).output("poly_angle", "x.2 : non 90 degree angle poly")
+rpm.ongrid(0.005).output("rpm_OFFGRID", "x.1b : OFFGRID vertex on rpm")
+rpm.with_angle(0 .. 45).output("rpm_angle", "x.3a : non 45 degree angle rpm")
+npc.ongrid(0.005).output("npc_OFFGRID", "x.1b : OFFGRID vertex on npc")
+npc.with_angle(0 .. 45).output("npc_angle", "x.3a : non 45 degree angle npc")
+nsdm.ongrid(0.005).output("nsdm_OFFGRID", "x.1b : OFFGRID vertex on nsdm")
+nsdm.with_angle(0 .. 45).output("nsdm_angle", "x.3a : non 45 degree angle nsdm")
+psdm.ongrid(0.005).output("psdm_OFFGRID", "x.1b : OFFGRID vertex on psdm")
+psdm.with_angle(0 .. 45).output("psdm_angle", "x.3a : non 45 degree angle psdm")
+licon.ongrid(0.005).output("licon_OFFGRID", "x.1b : OFFGRID vertex on licon")
+licon.with_angle(0 .. 90).output("licon_angle", "x.2 : non 90 degree angle licon")
+li.ongrid(0.005).output("li_OFFGRID", "x.1b : OFFGRID vertex on li")
+li.with_angle(0 .. 45).output("li_angle", "x.3a : non 45 degree angle li")
+mcon.ongrid(0.005).output("ct_OFFGRID", "x.1b : OFFGRID vertex on mcon")
+mcon.with_angle(0 .. 90).output("ct_angle", "x.2 : non 90 degree angle mcon")
+vpp.ongrid(0.005).output("vpp_OFFGRID", "x.1b : OFFGRID vertex on vpp")
+vpp.with_angle(0 .. 45).output("vpp_angle", "x.3a : non 45 degree angle vpp")
+m1.ongrid(0.005).output("m1_OFFGRID", "x.1b : OFFGRID vertex on m1")
+m1.with_angle(0 .. 45).output("m1_angle", "x.3a : non 45 degree angle m1")
+via.ongrid(0.005).output("via_OFFGRID", "x.1b : OFFGRID vertex on via")
+via.with_angle(0 .. 90).output("via_angle", "x.2 : non 90 degree angle via")
+m2.ongrid(0.005).output("m2_OFFGRID", "x.1b : OFFGRID vertex on m2")
+m2.with_angle(0 .. 45).output("m2_angle", "x.3a : non 45 degree angle m2")
+via2.ongrid(0.005).output("via2_OFFGRID", "x.1b : OFFGRID vertex on via2")
+via2.with_angle(0 .. 90).output("via2_angle", "x.2 : non 90 degree angle via2")
+m3.ongrid(0.005).output("m3_OFFGRID", "x.1b : OFFGRID vertex on m3")
+m3.with_angle(0 .. 45).output("m3_angle", "x.3a : non 45 degree angle m3")
+via3.ongrid(0.005).output("via3_OFFGRID", "x.1b : OFFGRID vertex on via3")
+via3.with_angle(0 .. 90).output("via3_angle", "x.2 : non 90 degree angle via3")
+nsm.ongrid(0.005).output("nsm_OFFGRID", "x.1b : OFFGRID vertex on nsm")
+nsm.with_angle(0 .. 45).output("nsm_angle", "x.3a : non 45 degree angle nsm")
+m4.ongrid(0.005).output("m4_OFFGRID", "x.1b : OFFGRID vertex on m4")
+m4.with_angle(0 .. 45).output("m4_angle", "x.3a : non 45 degree angle m4")
+via4.ongrid(0.005).output("via4_OFFGRID", "x.1b : OFFGRID vertex on via4")
+via4.with_angle(0 .. 90).output("via4_angle", "x.2 : non 90 degree angle via4")
+m5.ongrid(0.005).output("m5_OFFGRID", "x.1b : OFFGRID vertex on m5")
+m5.with_angle(0 .. 45).output("m5_angle", "x.3a : non 45 degree angle m5")
+pad.ongrid(0.005).output("pad_OFFGRID", "x.1b : OFFGRID vertex on pad")
+pad.with_angle(0 .. 45).output("pad_angle", "x.3a : non 45 degree angle pad")
+mf.ongrid(0.005).output("mf_OFFGRID", "x.1b : OFFGRID vertex on mf")
+mf.with_angle(0 .. 90).output("mf_angle", "x.2 : non 90 degree angle mf")
+hvi.ongrid(0.005).output("hvi_OFFGRID", "x.1b : OFFGRID vertex on hvi")
+hvi.with_angle(0 .. 45).output("hvi_angle", "x.3a : non 45 degree angle hvi")
+hvntm.ongrid(0.005).output("hvntm_OFFGRID", "x.1b : OFFGRID vertex on hvntm")
+hvntm.with_angle(0 .. 45).output("hvntm_angle", "x.3a : non 45 degree angle hvntm")
+vhvi.ongrid(0.005).output("vhvi_OFFGRID", "x.1b : OFFGRID vertex on vhvi")
+vhvi.with_angle(0 .. 45).output("vhvi_angle", "x.3a : non 45 degree angle vhvi")
+uhvi.ongrid(0.005).output("uhvi_OFFGRID", "x.1b : OFFGRID vertex on uhvi")
+uhvi.with_angle(0 .. 45).output("uhvi_angle", "x.3a : non 45 degree angle uhvi")
+pwell_rs.ongrid(0.005).output("pwell_rs_OFFGRID", "x.1b : OFFGRID vertex on pwell_rs")
+pwell_rs.with_angle(0 .. 45).output("pwell_rs_angle", "x.3a : non 45 degree angle pwell_rs")
+areaid_re.ongrid(0.005).output("areaid_re_OFFGRID", "x.1b : OFFGRID vertex on areaid.re")
+
+end #OFFGRID</text>
+</klayout-macro>

alu_w32_5ops_sky130_1000mhz/flow/drc_report.rpt

@@ -0,0 +1,892 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/drc_deck_patched.lydrc'</generator>
+ <top-cell>alu_w32_5ops</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.1a</name>
+   <description>li.1a : min. li width for the cells s8rf2_xcmvpp_hd5_* : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3a</name>
+   <description>li.3a : min. li spacing for the cells s8rf2_xcmvpp_hd5_* : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 opposite edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1 : minimum/maximum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 opposite edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4c.5c</name>
+   <description>via.4c.5c : m1 must enclose all via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : minimum/maximum width of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1b</name>
+   <description>via.1b : minimum/maximum width of via in areaid.mt: 0.15um or 0.23um or 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4b</name>
+   <description>via.4b : min. m1 enclosure of 0.23um via : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via1.5a</name>
+   <description>via1.5a : min. m1 enclosure of 0.15um via of 2 opposite edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via1.5b</name>
+   <description>via1.5b : min. m1 enclosure of 0.23um via of 2 opposite edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.via</name>
+   <description>m2.via : m2 must enclose via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 opposite edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2</name>
+   <description>via2 : m2 must enclose all via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : minimum/maximum width of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1b</name>
+   <description>via2.1b : minimum/maximum width of via2 in areaid.mt: 0.2um or 1.2um or 1.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4a</name>
+   <description>via2.4a : min. m2 enclosure of 1.5um via2 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m2 enclosure of via2 of 2 opposite edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3ab</name>
+   <description>m3.3ab : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.6</name>
+   <description>m3.6 : min. m3 area : 0.24um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.via2</name>
+   <description>m3.via2 : m3 must enclose via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3</name>
+   <description>via3 : m3 must enclose all via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1a</name>
+   <description>via3.1a : minimum/maximum width of via3 in areaid.mt: 0.2um or 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m2 enclosure of via3 of 2 opposite edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4</name>
+   <description>m4.4 : min. m4 area : 0.24um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.via3</name>
+   <description>m4.via3 : m4 must enclose via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1a</name>
+   <description>via4.1a : minimum/maximum width of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4</name>
+   <description>via4 : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.via4</name>
+   <description>m5.via4 : m5 must enclose via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m4.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.1</name>
+   <description>nsm.1 : min. nsm width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.2</name>
+   <description>nsm.2 : min. nsm spacing : 4.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.4</name>
+   <description>nsm.4 : min. nsm enclosure of cfom : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.3</name>
+   <description>nsm.3 : min. nsm spacing to cfom : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>x.3a : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>x.3a : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_angle</name>
+   <description>x.3a : non 45 degree angle pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_angle</name>
+   <description>x.3a : non 45 degree angle pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_angle</name>
+   <description>x.3a : non 45 degree angle hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_angle</name>
+   <description>x.3a : non 45 degree angle hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_angle</name>
+   <description>x.3a : non 45 degree angle lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_angle</name>
+   <description>x.3a : non 45 degree angle ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2c : non 45 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2c : non 45 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_angle</name>
+   <description>x.3a : non 45 degree angle tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_angle</name>
+   <description>x.2 : non 90 degree angle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_angle</name>
+   <description>x.3a : non 45 degree angle rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_angle</name>
+   <description>x.3a : non 45 degree angle npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_angle</name>
+   <description>x.3a : non 45 degree angle nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_angle</name>
+   <description>x.3a : non 45 degree angle psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_angle</name>
+   <description>x.2 : non 90 degree angle licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_angle</name>
+   <description>x.3a : non 45 degree angle li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_angle</name>
+   <description>x.2 : non 90 degree angle mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_angle</name>
+   <description>x.3a : non 45 degree angle vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_angle</name>
+   <description>x.3a : non 45 degree angle m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via_angle</name>
+   <description>x.2 : non 90 degree angle via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_angle</name>
+   <description>x.3a : non 45 degree angle m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>x.2 : non 90 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_angle</name>
+   <description>x.3a : non 45 degree angle m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
+   <description>x.2 : non 90 degree angle via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm_angle</name>
+   <description>x.3a : non 45 degree angle nsm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4_angle</name>
+   <description>x.3a : non 45 degree angle m4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4_angle</name>
+   <description>x.2 : non 90 degree angle via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5_angle</name>
+   <description>x.3a : non 45 degree angle m5</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad_angle</name>
+   <description>x.3a : non 45 degree angle pad</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>mf_angle</name>
+   <description>x.2 : non 90 degree angle mf</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvi_angle</name>
+   <description>x.3a : non 45 degree angle hvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvntm_angle</name>
+   <description>x.3a : non 45 degree angle hvntm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_angle</name>
+   <description>x.3a : non 45 degree angle vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_angle</name>
+   <description>x.3a : non 45 degree angle uhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_angle</name>
+   <description>x.3a : non 45 degree angle pwell_rs</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>areaid_re_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on areaid.re</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
+ <cells>
+  <cell>
+   <name>alu_w32_5ops</name>
+   <variant/>
+   <layout-name/>
+   <references>
+   </references>
+  </cell>
+ </cells>
+ <items>
+ </items>
+</report-database>

alu_w32_5ops_sky130_1000mhz/flow/extracted/deepgate.json

@@ -0,0 +1 @@
+[{"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "gate_counts": {"or": 103, "nor": 54, "and": 109, "nand": 100, "xor": 41, "buf": 6, "xnor": 14}, "total_gates": 427, "netlist_file": "netlist.v", "netlist_size_bytes": 43144}]

alu_w32_5ops_sky130_1000mhz/flow/extracted/drc_labels.json

@@ -0,0 +1 @@
+[{"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "violation_type": "clean", "violation_count": 0}]

alu_w32_5ops_sky130_1000mhz/flow/extracted/mesoscale_blocks.json

@@ -0,0 +1 @@
+[{"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "block_id": "g0_0", "bounds": {"x1": 0, "y1": 0, "x2": 18386, "y2": 18386}, "cell_count": 39, "type_distribution": {"sky130_fd_sc_hd__fill_8": 27, "sky130_fd_sc_hd__fill_2": 3, "sky130_fd_sc_hd__decap_4": 6, "sky130_fd_sc_hd__tapvpwrvgnd_1": 3}, "density": 0.0455607476635514}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "block_id": "g0_1", "bounds": {"x1": 0, "y1": 18386, "x2": 18386, "y2": 36772}, "cell_count": 58, "type_distribution": {"sky130_fd_sc_hd__fill_2": 9, "sky130_fd_sc_hd__fill_1": 7, "sky130_fd_sc_hd__fill_8": 8, "sky130_fd_sc_hd__decap_4": 7, "sky130_fd_sc_hd__tapvpwrvgnd_1": 4, "sky130_fd_sc_hd__nor2_2": 1, "sky130_fd_sc_hd__nor3b_4": 1, "sky130_fd_sc_hd__or3b_4": 1, "sky130_fd_sc_hd__xor2_1": 4, "sky130_fd_sc_hd__lpflow_isobufsrc_1": 2, "sky130_fd_sc_hd__nor2_4": 1, "sky130_fd_sc_hd__lpflow_inputiso1p_1": 1, "sky130_fd_sc_hd__and2_4": 1, "sky130_fd_sc_hd__nand2_8": 1, "sky130_fd_sc_hd__nand2_1": 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alu_w32_5ops_sky130_1000mhz/flow/extracted/pin_access.json

@@ -0,0 +1 @@
+[{"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "pin_name": "VDD", "direction": "INOUT", "layer": "met5", "x": 36800, "y": 57120}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "pin_name": "VSS", "direction": "INOUT", "layer": "met5", "x": 36800, "y": 70720}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "pin_name": "a[0]", "direction": "INPUT", "layer": "met2", "x": 71990, "y": 73302}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "pin_name": "a[10]", "direction": "INPUT", "layer": "met2", "x": 71070, "y": 73302}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "pin_name": "a[11]", "direction": "INPUT", "layer": "met2", "x": 70150, "y": 73302}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "pin_name": "a[12]", "direction": "INPUT", "layer": "met2", "x": 69230, "y": 73302}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "pin_name": "a[13]", "direction": "INPUT", "layer": "met2", "x": 68310, "y": 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alu_w32_5ops_sky130_1000mhz/flow/extracted/power_grid.json

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{"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 330, "coords": [{"x": 14160, "y": 51680}, {"x": 15740, "y": 51680}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 0, "coords": [{"x": 14950, "y": 51680}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 370, "coords": [{"x": 14180, "y": 51680}, {"x": 15720, "y": 51680}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 0, "coords": [{"x": 14950, "y": 51680}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met1", "width": 0, "coords": [{"x": 14950, "y": 51680}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 330, "coords": [{"x": 14160, "y": 46240}, {"x": 15740, "y": 46240}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 0, "coords": [{"x": 14950, "y": 46240}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 370, "coords": [{"x": 14180, "y": 46240}, {"x": 15720, "y": 46240}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 0, "coords": [{"x": 14950, "y": 46240}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met1", "width": 0, "coords": [{"x": 14950, "y": 46240}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 330, "coords": [{"x": 14160, "y": 40800}, {"x": 15740, "y": 40800}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 0, "coords": [{"x": 14950, "y": 40800}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 370, "coords": [{"x": 14180, "y": 40800}, {"x": 15720, "y": 40800}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 0, "coords": [{"x": 14950, "y": 40800}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met1", "width": 0, "coords": [{"x": 14950, "y": 40800}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 330, "coords": [{"x": 14160, "y": 35360}, {"x": 15740, "y": 35360}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 0, "coords": [{"x": 14950, "y": 35360}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 370, "coords": [{"x": 14180, "y": 35360}, {"x": 15720, "y": 35360}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 0, "coords": [{"x": 14950, "y": 35360}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met1", "width": 0, "coords": [{"x": 14950, "y": 35360}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 330, "coords": [{"x": 14160, "y": 29920}, {"x": 15740, "y": 29920}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 0, "coords": [{"x": 14950, "y": 29920}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 370, "coords": [{"x": 14180, "y": 29920}, {"x": 15720, "y": 29920}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 0, "coords": [{"x": 14950, "y": 29920}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met1", "width": 0, "coords": [{"x": 14950, "y": 29920}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 330, "coords": [{"x": 14160, "y": 24480}, {"x": 15740, "y": 24480}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 0, "coords": [{"x": 14950, "y": 24480}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 370, "coords": [{"x": 14180, "y": 24480}, {"x": 15720, "y": 24480}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 0, "coords": [{"x": 14950, "y": 24480}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met1", "width": 0, "coords": [{"x": 14950, "y": 24480}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 330, "coords": [{"x": 14160, "y": 19040}, {"x": 15740, "y": 19040}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 0, "coords": [{"x": 14950, "y": 19040}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 370, "coords": [{"x": 14180, "y": 19040}, {"x": 15720, "y": 19040}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 0, "coords": [{"x": 14950, "y": 19040}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met1", "width": 0, "coords": [{"x": 14950, "y": 19040}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 330, "coords": [{"x": 14160, "y": 13600}, {"x": 15740, "y": 13600}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 0, "coords": [{"x": 14950, "y": 13600}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 370, "coords": [{"x": 14180, "y": 13600}, {"x": 15720, "y": 13600}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 0, "coords": [{"x": 14950, "y": 13600}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met1", "width": 0, "coords": [{"x": 14950, "y": 13600}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 330, "coords": [{"x": 14160, "y": 8160}, {"x": 15740, "y": 8160}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 0, "coords": [{"x": 14950, "y": 8160}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 370, "coords": [{"x": 14180, "y": 8160}, {"x": 15720, "y": 8160}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 0, "coords": [{"x": 14950, "y": 8160}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met1", "width": 0, "coords": [{"x": 14950, "y": 8160}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 330, "coords": [{"x": 14160, "y": 2720}, {"x": 15740, "y": 2720}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met3", "width": 0, "coords": [{"x": 14950, "y": 2720}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 370, "coords": [{"x": 14180, "y": 2720}, {"x": 15720, "y": 2720}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met2", "width": 0, "coords": [{"x": 14950, "y": 2720}]}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "net": "VSS", "layer": "met1", "width": 0, "coords": [{"x": 14950, "y": 2720}]}]

alu_w32_5ops_sky130_1000mhz/flow/extracted/timing_contexts.json

@@ -0,0 +1 @@
+[{"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "freq_mhz": 1000, "wns_ns": null, "tns_ns": null, "utilization": 0.58, "num_instances": 856, "area_um2": 2798.0, "multi_corner": ["ff_n40C_1v95 (fast)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "tt_025C_1v80 (typical) WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "ss_n40C_1v40 (slow)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "ff_n40C_1v95 (fast)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "tt_025C_1v80 (typical) WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "ss_n40C_1v40 (slow)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]"], "power_mw": null, "drc_clean": true, "lvs_clean": true}]

alu_w32_5ops_sky130_1000mhz/flow/extracted/trajectory_snapshots.json

@@ -0,0 +1 @@
+[{"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "phase": 1, "label": "Step 1/3: Synthesis", "type": "phase_start"}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "phase": 1, "cells": 389, "type": "synth_result"}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "phase": 1, "duration_s": 0.6, "type": "phase_end"}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "phase": 2, "label": "Step 2/3: Place and Route", "type": "phase_start"}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "phase": 2, "instances": 856, "utilization": 0.58, "type": "pnr_result"}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "phase": 2, "duration_s": 292.6, "type": "phase_end"}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "phase": 3, "label": "Step 3/3: GDS Generation", "type": "phase_start"}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "phase": 3, "duration_s": 303.92, "type": "phase_end"}, {"run_id": "alu_w32_5ops_sky130_1000mhz", "pdk": "sky130", "phase": 3, "signoff": "PASS", "type": "signoff_result"}]

alu_w32_5ops_sky130_1000mhz/flow/flow_log.txt

@@ -0,0 +1,94 @@
+╔══════════════════════════════════════════╗
+║          Zyphar Flow v1.0.0              ║
+║    Complete RTL-to-GDSII Toolchain       ║
+╚══════════════════════════════════════════╝
+
+Configuration:
+  Input:     /tmp/datagen_designs/alu_w32_5ops/alu_w32_5ops.v
+  Top:       alu_w32_5ops
+  PDK:       Sky130
+  Frequency: 1000 MHz
+  Clock:     clk
+  Output:    /tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow
+
+Starting flow...
+
+=== Step 1/3: Synthesis ===
+Synthesis complete: 389 cells, 0.00 um^2
+  Wires: 361, Modules: 1
+  Netlist: /tmp/zyphar_netlist_959439.v
+  Duration: 0.6s
+
+--- CDC Analysis ---
+  No clock domain crossings detected
+
+--- Native Re-Optimization ---
+  Skipped (no Liberty file provided, use --liberty)
+
+=== Step 2/3: Place and Route ===
+  Input netlist: /tmp/zyphar_netlist_959439.v
+  PDK: Sky130, Freq: 1000 MHz, Clock: clk
+  Utilization: 45%, Aspect ratio: 1.0, Placement density: 0.80 (auto)
+  PDN: true, Detailed route: true, Fillers: true, Antenna: true
+PnR complete: 856 instances, 0.58 utilization
+  DEF: /tmp/zyphar_pnr_959439.def
+  WNS: N/A (combinational)
+  Duration: 292.6s
+
+--- Multi-Corner STA ---
+  Using post-PnR netlist with SPEF back-annotation
+  ff_n40C_1v95 (fast)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+  tt_025C_1v80 (typical) WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+  ss_n40C_1v40 (slow)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+
+--- Power Analysis ---
+  Power analysis skipped: No Liberty file available (use --liberty or set SKY130_LIBERTY)
+
+=== Step 3/3: GDS Generation ===
+GDS generation complete: /tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/alu_w32_5ops.gds
+
+=== Signoff Checks ===
+
+--- DRC ---
+  DRC: CLEAN
+
+--- LVS ---
+  LVS: CLEAN
+
+═══════════════════════════════════════════
+                  RESULTS                  
+═══════════════════════════════════════════
+
+Synthesis:
+  Cells:     389
+  Netlist:   /tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/netlist.v
+
+Place & Route:
+  DEF:       /tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/output.def
+  WNS:       N/A (combinational)
+  Util:      58.0%
+  Instances: 856
+  Area:      2798.00 um^2
+
+GDSII:       /tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/alu_w32_5ops.gds
+
+Multi-Corner STA:
+  ff_n40C_1v95 (fast)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+  tt_025C_1v80 (typical) WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+  ss_n40C_1v40 (slow)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+
+SPEF:        /tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/alu_w32_5ops.spef
+
+Duration:    303.92s
+
+Signoff:
+  Timing:         N/A (combinational)
+  DRC:            CLEAN
+  DRC report:     /tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/drc_report.rpt
+  LVS:            CLEAN
+  LVS report:     /tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/lvs_report.lyrdb
+
+  SIGNOFF: PASS
+
+Flow completed successfully!
+

alu_w32_5ops_sky130_1000mhz/flow/klayout_lvs.log

@@ -0,0 +1,750 @@
+=== stdout ===
+"polygons" in: lvs_deck_patched.lylvs:49
+    Polygons (raw): 1 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 589.00M
+"polygons" in: lvs_deck_patched.lylvs:50
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 589.00M
+"polygons" in: lvs_deck_patched.lylvs:51
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 589.00M
+"polygons" in: lvs_deck_patched.lylvs:52
+    Polygons (raw): 446 (flat)  47 (hierarchical)
+    Elapsed: 0.000s  Memory: 589.00M
+"input" in: lvs_deck_patched.lylvs:53
+    Polygons (raw): 392 (flat)  46 (hierarchical)
+    Elapsed: 0.000s  Memory: 589.00M
+"polygons" in: lvs_deck_patched.lylvs:54
+    Polygons (raw): 398 (flat)  47 (hierarchical)
+    Elapsed: 0.000s  Memory: 589.00M
+"input" in: lvs_deck_patched.lylvs:55
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 589.00M
+"input" in: lvs_deck_patched.lylvs:56
+    Polygons (raw): 392 (flat)  46 (hierarchical)
+    Elapsed: 0.000s  Memory: 589.00M
+"polygons" in: lvs_deck_patched.lylvs:57
+    Polygons (raw): 865 (flat)  110 (hierarchical)
+    Elapsed: 0.000s  Memory: 589.00M
+"polygons" in: lvs_deck_patched.lylvs:58
+    Polygons (raw): 108 (flat)  2 (hierarchical)
+    Elapsed: 0.000s  Memory: 589.00M
+"polygons" in: lvs_deck_patched.lylvs:59
+    Polygons (raw): 500 (flat)  48 (hierarchical)
+    Elapsed: 0.010s  Memory: 589.00M
+"polygons" in: lvs_deck_patched.lylvs:60
+    Polygons (raw): 500 (flat)  48 (hierarchical)
+    Elapsed: 0.000s  Memory: 589.00M
+"polygons" in: lvs_deck_patched.lylvs:61
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 589.00M
+"polygons" in: lvs_deck_patched.lylvs:62
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"polygons" in: lvs_deck_patched.lylvs:63
+    Polygons (raw): 446 (flat)  47 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"polygons" in: lvs_deck_patched.lylvs:64
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"polygons" in: lvs_deck_patched.lylvs:65
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"polygons" in: lvs_deck_patched.lylvs:66
+    Polygons (raw): 446 (flat)  47 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"polygons" in: lvs_deck_patched.lylvs:67
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"polygons" in: lvs_deck_patched.lylvs:68
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"polygons" in: lvs_deck_patched.lylvs:69
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"polygons" in: lvs_deck_patched.lylvs:70
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"polygons" in: lvs_deck_patched.lylvs:71
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"polygons" in: lvs_deck_patched.lylvs:72
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"polygons" in: lvs_deck_patched.lylvs:73
+    Polygons (raw): 1444 (flat)  235 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"input" in: lvs_deck_patched.lylvs:74
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 590.00M
+"polygons" in: lvs_deck_patched.lylvs:75
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 591.00M
+"polygons" in: lvs_deck_patched.lylvs:76
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 591.00M
+"polygons" in: lvs_deck_patched.lylvs:77
+    Polygons (raw): 7310 (flat)  1145 (hierarchical)
+    Elapsed: 0.000s  Memory: 591.00M
+"polygons" in: lvs_deck_patched.lylvs:78
+    Polygons (raw): 402 (flat)  51 (hierarchical)
+    Elapsed: 0.000s  Memory: 591.00M
+"polygons" in: lvs_deck_patched.lylvs:79
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 591.00M
+"polygons" in: lvs_deck_patched.lylvs:80
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 591.00M
+"polygons" in: lvs_deck_patched.lylvs:81
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 591.00M
+"polygons" in: lvs_deck_patched.lylvs:82
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 591.00M
+"polygons" in: lvs_deck_patched.lylvs:83
+    Polygons (raw): 5248 (flat)  585 (hierarchical)
+    Elapsed: 0.000s  Memory: 591.00M
+"input" in: lvs_deck_patched.lylvs:84
+    Polygons (raw): 2190 (flat)  376 (hierarchical)
+    Elapsed: 0.000s  Memory: 591.00M
+"polygons" in: lvs_deck_patched.lylvs:85
+    Polygons (raw): 2391 (flat)  400 (hierarchical)
+    Elapsed: 0.010s  Memory: 591.00M
+"polygons" in: lvs_deck_patched.lylvs:86
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 592.00M
+"polygons" in: lvs_deck_patched.lylvs:87
+    Polygons (raw): 5649 (flat)  650 (hierarchical)
+    Elapsed: 0.000s  Memory: 592.00M
+"polygons" in: lvs_deck_patched.lylvs:88
+    Polygons (raw): 5989 (flat)  2154 (hierarchical)
+    Elapsed: 0.000s  Memory: 592.00M
+"input" in: lvs_deck_patched.lylvs:89
+    Polygons (raw): 892 (flat)  94 (hierarchical)
+    Elapsed: 0.000s  Memory: 592.00M
+"polygons" in: lvs_deck_patched.lylvs:90
+    Polygons (raw): 904 (flat)  96 (hierarchical)
+    Elapsed: 0.000s  Memory: 592.00M
+"polygons" in: lvs_deck_patched.lylvs:91
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 592.00M
+"polygons" in: lvs_deck_patched.lylvs:92
+    Polygons (raw): 1744 (flat)  6 (hierarchical)
+    Elapsed: 0.000s  Memory: 592.00M
+"polygons" in: lvs_deck_patched.lylvs:93
+    Polygons (raw): 3298 (flat)  1417 (hierarchical)
+    Elapsed: 0.010s  Memory: 592.00M
+"input" in: lvs_deck_patched.lylvs:94
+    Polygons (raw): 78 (flat)  78 (hierarchical)
+    Elapsed: 0.000s  Memory: 593.00M
+"polygons" in: lvs_deck_patched.lylvs:95
+    Polygons (raw): 78 (flat)  78 (hierarchical)
+    Elapsed: 0.000s  Memory: 593.00M
+"polygons" in: lvs_deck_patched.lylvs:96
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 593.00M
+"polygons" in: lvs_deck_patched.lylvs:97
+    Polygons (raw): 596 (flat)  5 (hierarchical)
+    Elapsed: 0.000s  Memory: 593.00M
+"polygons" in: lvs_deck_patched.lylvs:98
+    Polygons (raw): 946 (flat)  394 (hierarchical)
+    Elapsed: 0.000s  Memory: 593.00M
+"input" in: lvs_deck_patched.lylvs:99
+    Polygons (raw): 21 (flat)  21 (hierarchical)
+    Elapsed: 0.000s  Memory: 593.00M
+"polygons" in: lvs_deck_patched.lylvs:100
+    Polygons (raw): 21 (flat)  21 (hierarchical)
+    Elapsed: 0.000s  Memory: 593.00M
+"polygons" in: lvs_deck_patched.lylvs:101
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 593.00M
+"polygons" in: lvs_deck_patched.lylvs:102
+    Polygons (raw): 350 (flat)  5 (hierarchical)
+    Elapsed: 0.000s  Memory: 593.00M
+"polygons" in: lvs_deck_patched.lylvs:103
+    Polygons (raw): 225 (flat)  60 (hierarchical)
+    Elapsed: 0.000s  Memory: 594.00M
+"input" in: lvs_deck_patched.lylvs:104
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 594.00M
+"polygons" in: lvs_deck_patched.lylvs:105
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 594.00M
+"polygons" in: lvs_deck_patched.lylvs:106
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 594.00M
+"polygons" in: lvs_deck_patched.lylvs:107
+    Polygons (raw): 13 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 594.00M
+"polygons" in: lvs_deck_patched.lylvs:108
+    Polygons (raw): 18 (flat)  6 (hierarchical)
+    Elapsed: 0.000s  Memory: 594.00M
+"input" in: lvs_deck_patched.lylvs:109
+    Polygons (raw): 2 (flat)  2 (hierarchical)
+    Elapsed: 0.000s  Memory: 594.00M
+"polygons" in: lvs_deck_patched.lylvs:110
+    Polygons (raw): 5 (flat)  5 (hierarchical)
+    Elapsed: 0.000s  Memory: 594.00M
+"polygons" in: lvs_deck_patched.lylvs:111
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 594.00M
+"polygons" in: lvs_deck_patched.lylvs:112
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 594.00M
+"input" in: lvs_deck_patched.lylvs:113
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 594.00M
+"polygons" in: lvs_deck_patched.lylvs:114
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 594.00M
+"polygons" in: lvs_deck_patched.lylvs:115
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:116
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:117
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:118
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:119
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:120
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:121
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:122
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:123
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 595.00M
+"polygons" in: lvs_deck_patched.lylvs:126
+    Polygons (raw): 392 (flat)  46 (hierarchical)
+    Elapsed: 0.000s  Memory: 595.00M
+"&" in: lvs_deck_patched.lylvs:130
+    Polygons (raw): 443 (flat)  53 (hierarchical)
+    Elapsed: 0.010s  Memory: 1137.00M
+"&" in: lvs_deck_patched.lylvs:130
+    Polygons (raw): 443 (flat)  53 (hierarchical)
+    Elapsed: 0.010s  Memory: 1147.00M
+"&" in: lvs_deck_patched.lylvs:131
+    Polygons (raw): 54 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 1158.00M
+"&" in: lvs_deck_patched.lylvs:131
+    Polygons (raw): 54 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 1168.00M
+"&" in: lvs_deck_patched.lylvs:132
+    Polygons (raw): 1471 (flat)  251 (hierarchical)
+    Elapsed: 0.010s  Memory: 1148.00M
+"-" in: lvs_deck_patched.lylvs:133
+    Polygons (raw): 1914 (flat)  304 (hierarchical)
+    Elapsed: 0.010s  Memory: 1138.00M
+"-" in: lvs_deck_patched.lylvs:134
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1158.00M
+"-" in: lvs_deck_patched.lylvs:134
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"-" in: lvs_deck_patched.lylvs:134
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"-" in: lvs_deck_patched.lylvs:135
+    Polygons (raw): 446 (flat)  47 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"-" in: lvs_deck_patched.lylvs:135
+    Polygons (raw): 446 (flat)  47 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"&" in: lvs_deck_patched.lylvs:135
+    Polygons (raw): 1471 (flat)  251 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"-" in: lvs_deck_patched.lylvs:136
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1148.00M
+"-" in: lvs_deck_patched.lylvs:136
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"&" in: lvs_deck_patched.lylvs:136
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1138.00M
+"-" in: lvs_deck_patched.lylvs:138
+    Polygons (raw): 416 (flat)  53 (hierarchical)
+    Elapsed: 0.010s  Memory: 1159.00M
+"&" in: lvs_deck_patched.lylvs:138
+    Polygons (raw): 414 (flat)  51 (hierarchical)
+    Elapsed: 0.010s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:139
+    Polygons (raw): 54 (flat)  1 (hierarchical)
+    Elapsed: 0.010s  Memory: 1159.00M
+"&" in: lvs_deck_patched.lylvs:139
+    Polygons (raw): 54 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 1159.00M
+"&" in: lvs_deck_patched.lylvs:140
+    Polygons (raw): 1468 (flat)  250 (hierarchical)
+    Elapsed: 0.000s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:141
+    Polygons (raw): 1882 (flat)  301 (hierarchical)
+    Elapsed: 0.000s  Memory: 1149.00M
+"-" in: lvs_deck_patched.lylvs:142
+    Polygons (raw): 1468 (flat)  250 (hierarchical)
+    Elapsed: 0.000s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:142
+    Polygons (raw): 1468 (flat)  250 (hierarchical)
+    Elapsed: 0.000s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:142
+    Polygons (raw): 1468 (flat)  250 (hierarchical)
+    Elapsed: 0.000s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:143
+    Polygons (raw): 1468 (flat)  250 (hierarchical)
+    Elapsed: 0.000s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:143
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1139.00M
+"&" in: lvs_deck_patched.lylvs:143
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1139.00M
+"-" in: lvs_deck_patched.lylvs:144
+    Polygons (raw): 1468 (flat)  250 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"-" in: lvs_deck_patched.lylvs:144
+    Polygons (raw): 1468 (flat)  250 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"&" in: lvs_deck_patched.lylvs:144
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.010s  Memory: 1140.00M
+"-" in: lvs_deck_patched.lylvs:145
+    Polygons (raw): 1468 (flat)  250 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"&" in: lvs_deck_patched.lylvs:145
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"&" in: lvs_deck_patched.lylvs:145
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1140.00M
+"extract_devices" in: lvs_deck_patched.lylvs:151
+    Elapsed: 0.010s  Memory: 1141.00M
+"extract_devices" in: lvs_deck_patched.lylvs:152
+    Elapsed: 0.020s  Memory: 1141.00M
+"extract_devices" in: lvs_deck_patched.lylvs:153
+    Elapsed: 0.010s  Memory: 1142.00M
+"extract_devices" in: lvs_deck_patched.lylvs:156
+    Elapsed: 0.020s  Memory: 1142.00M
+"extract_devices" in: lvs_deck_patched.lylvs:157
+    Elapsed: 0.010s  Memory: 1142.00M
+"extract_devices" in: lvs_deck_patched.lylvs:158
+    Elapsed: 0.010s  Memory: 1142.00M
+"extract_devices" in: lvs_deck_patched.lylvs:159
+    Elapsed: 0.020s  Memory: 1142.00M
+"netlist" in: lvs_deck_patched.lylvs:199
+    Elapsed: 0.140s  Memory: 1148.00M
+Flatten layout cell (no schematic): VIA_via4_5_1600_480_1_4_400_400
+Flatten layout cell (no schematic): VIA_via3_4_1600_480_1_4_400_400
+Flatten layout cell (no schematic): VIA_via2_3_1600_480_1_5_320_320
+Flatten layout cell (no schematic): VIA_L1M1_PR_MR
+Flatten layout cell (no schematic): VIA_M1M2_PR
+Flatten layout cell (no schematic): VIA_M2M3_PR
+Flatten layout cell (no schematic): VIA_L1M1_PR
+Flatten layout cell (no schematic): VIA_via5_6_1600_1600_1_1_1600_1600
+Flatten layout cell (no schematic): VIA_M3M4_PR
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BO_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BO_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BO_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A222OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4BB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4BB_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4BB_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFBUF_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFBUF_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFINV_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFINV_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_12
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S15_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S15_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S18_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S18_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S25_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S25_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S50_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S50_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINVLP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINVLP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_12
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_3
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_6
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFBBN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFBBN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFBBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DIODE_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLCLKP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLCLKP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLCLKP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTN_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXBN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXBN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTN_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYGATE4SD1_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYGATE4SD2_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYGATE4SD3_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYMETAL6S2S_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYMETAL6S4S_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYMETAL6S6S_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EDFXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EDFXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FAHCIN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FAHCON_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FAH_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FA_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FA_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FA_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__HA_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__HA_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__HA_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_12
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_6
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_BLEEDER_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MACRO_SPARECELL
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CONB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MAJ3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MAJ3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2I_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2I_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2I_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX4_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4BB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4BB_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4BB_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4BB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4BB_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4BB_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BAI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BAI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BAI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BA_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BA_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BA_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4BB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4BB_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4BB_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__PROBEC_P_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__PROBE_P_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFBBN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFBBN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFBBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDLCLKP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDLCLKP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDLCLKP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAPVGND2_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAPVGND_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR3_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR3_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR3_4
+Writing netlist: /tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/lvs_extracted.cir ..
+Writing LVS database: /tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/lvs_report.lyrdb ..
+Total elapsed: 0.740s  Memory: 1156.00M
+INFO : Congratulations! Netlists match.
+
+=== stderr ===

alu_w32_5ops_sky130_1000mhz/flow/lvs_cleaned.gds.gz

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:fbf35a8ee8d1d1f46e8e74697472e14f2379abfde623ca0a8e5336690cd7f5bc
+size 108727

alu_w32_5ops_sky130_1000mhz/flow/lvs_deck_patched.lylvs

@@ -0,0 +1,295 @@
+<?xml version="1.0" encoding="utf-8"?>
+<klayout-macro>
+ <description/>
+ <version/>
+ <category>lvs</category>
+ <prolog/>
+ <epilog/>
+ <doc/>
+ <autorun>false</autorun>
+ <autorun-early>false</autorun-early>
+ <shortcut/>
+ <show-in-menu>true</show-in-menu>
+ <group-name>lvs_scripts</group-name>
+ <menu-path>tools_menu.lvs.end</menu-path>
+ <interpreter>dsl</interpreter>
+ <dsl-interpreter-name>lvs-dsl-xml</dsl-interpreter-name>
+ <text>#
+# Extraction for SKY130
+#
+############################
+
+# optionnal for a batch launch :   klayout -b -rd in_gds=my_layout.gds -rd report_file=my_report.lyrdb -rd cdl_file=reference_netlist.cir -rd target_netlist=extracted_netlist.cir -r sky130.lylvs
+if $in_gds
+  source($in_gds)
+end
+
+if $report_file
+  report_lvs($report_file)
+else
+  report_lvs("lvs_report.lvsdb")
+end
+
+if $cdl_file
+#reference netlist
+   schematic($cdl_file)
+else 
+   schematic("sky130hd.cdl")
+end
+
+# true: use net names instead of numbers
+# false: use numbers for nets
+spice_with_net_names = true
+
+# true: put in comments with details
+# false: no comments
+spice_with_comments = false
+
+if $target_netlist
+  target_netlist($target_netlist)
+else
+   # target_netlist("netlist.cir", write_spice(spice_with_net_names, spice_with_comments), "The netlist comment goes here.") 
+   target_netlist(File.join(File.dirname(RBA::CellView::active.filename), source.cell_name+"_extracted.cir"), write_spice(spice_with_net_names, spice_with_comments),  "Extracted by KLayout on : #{Time.now.strftime("%d/%m/%Y %H:%M")}")
+end
+
+# Hierarchical mode
+deep
+# Use 4 CPU cores
+threads(4)
+# Print details
+verbose(true)
+
+
+# layers definitions
+########################
+BOUND  = polygons(235, 4)
+DNWELL  = polygons(64, 18)
+PWRES  = polygons(64, 13)
+NWELL  = polygons(64, 20)
+NWELLTXT  = input(64, 5)
+NWELLPIN  = polygons(64, 16)
+SUBTXT  = input(122, 5)
+SUBPIN  = input(64, 59)
+DIFF  = polygons(65, 20)
+TAP  = polygons(65, 44)
+PSDM  = polygons(94, 20)
+NSDM  = polygons(93, 44)
+LVTN  = polygons(125, 44)
+HVTR  = polygons(18, 20)
+HVTP  = polygons(78, 44)
+SONOS  = polygons(80, 20)
+COREID  = polygons(81, 2)
+STDCELL  = polygons(81, 4)
+NPNID  = polygons(82, 20)
+PNPID  = polygons(82, 44)
+RPM  = polygons(86, 20)
+URPM  = polygons(79, 20)
+LDNTM  = polygons(11, 44)
+HVNTM  = polygons(125, 20)
+POLY  = polygons(66, 20)
+POLYTXT  = input(66, 5)
+POLYPIN  = polygons(66, 16)
+HVI  = polygons(75, 20)
+LICON  = polygons(66, 44)
+NPC  = polygons(95, 20)
+DIFFRES  = polygons(65, 13)
+POLYRES  = polygons(66, 13)
+POLYSHO  = polygons(66, 15)
+DIODE  = polygons(81, 23)
+LI  = polygons(67, 20)
+LITXT  = input(67, 5)
+LIPIN  = polygons(67, 16)
+LIRES  = polygons(67, 13)
+MCON  = polygons(67, 44)
+MET1  = polygons(68, 20)
+MET1TXT  = input(68, 5)
+MET1PIN  = polygons(68, 16)
+MET1RES  = polygons(68, 13)
+VIA1  = polygons(68, 44)
+MET2  = polygons(69, 20)
+MET2TXT  = input(69, 5)
+MET2PIN  = polygons(69, 16)
+MET2RES  = polygons(69, 13)
+VIA2  = polygons(69, 44)
+MET3  = polygons(70, 20)
+MET3TXT  = input(70, 5)
+MET3PIN  = polygons(70, 16)
+MET3RES  = polygons(70, 13)
+VIA3  = polygons(70, 44)
+MET4  = polygons(71, 20)
+MET4TXT  = input(71, 5)
+MET4PIN  = polygons(71, 16)
+MET4RES  = polygons(71, 13)
+VIA4  = polygons(71, 44)
+MET5  = polygons(72, 20)
+MET5TXT  = input(72, 5)
+MET5PIN  = polygons(72, 16)
+MET5RES  = polygons(72, 13)
+RDL  = polygons(74, 20)
+RDLTXT  = input(74, 5)
+RDLPIN  = polygons(74, 16)
+GLASS  = polygons(76, 20)
+CAPM  = polygons(89, 44)
+CAPM2  = polygons(97, 44)
+LOWTAPD  = polygons(81, 14)
+FILLOBSM1  = polygons(62, 24)
+FILLOBSM2  = polygons(105, 52)
+FILLOBSM3  = polygons(107, 24)
+FILLOBSM4  = polygons(112, 4)
+NCM = polygons(92, 44)
+
+# Bulk layer for terminal provisioning
+SUB = polygons(236, 0)
+# SUB = polygon_layer
+
+# Computed layers
+PDIFF = DIFF &amp; NWELL &amp; PSDM
+NTAP = TAP &amp; NWELL &amp; NSDM
+PGATE = PDIFF &amp; POLY
+PSD = PDIFF - PGATE
+STD_PGATE = PGATE - HVTP - NCM - HVI
+HVT_PGATE = PGATE &amp; HVTP - NCM - HVI
+HV5_PGATE = PGATE - HVTP - NCM &amp; HVI
+  
+NDIFF = DIFF - NWELL &amp; NSDM
+PTAP = TAP - NWELL &amp; PSDM
+NGATE = NDIFF &amp; POLY
+NSD = NDIFF - NGATE
+STD_NGATE = NGATE - NCM - LVTN - HVI
+LVT_NGATE = NGATE - NCM &amp; LVTN - HVI
+HV5_NGATE = NGATE - NCM - LVTN &amp; HVI
+HV5NA_NGATE = NGATE - NCM &amp; LVTN &amp; HVI
+
+# drawing to physical
+device_scaling(1000000)
+
+# PMOS transistor device extraction
+extract_devices(mos4("pfet_01v8"), { "SD" =&gt; PSD, "G" =&gt; STD_PGATE, "tS" =&gt; PSD, "tD" =&gt; PSD, "tG" =&gt; POLY, "W" =&gt; NWELL })
+extract_devices(mos4("pfet_01v8_hvt"), { "SD" =&gt; PSD, "G" =&gt; HVT_PGATE, "tS" =&gt; PSD, "tD" =&gt; PSD, "tG" =&gt; POLY, "W" =&gt; NWELL })
+extract_devices(mos4("pfet_g5v0d10v5"), { "SD" =&gt; PSD, "G" =&gt; HV5_PGATE, "tS" =&gt; PSD, "tD" =&gt; PSD, "tG" =&gt; POLY, "W" =&gt; NWELL })
+
+# NMOS transistor device extraction
+extract_devices(mos4("nfet_01v8"), { "SD" =&gt; NSD, "G" =&gt; STD_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
+extract_devices(mos4("nfet_01v8_lvt"), { "SD" =&gt; NSD, "G" =&gt; LVT_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
+extract_devices(mos4("nfet_g5v0d10v5"), { "SD" =&gt; NSD, "G" =&gt; HV5_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
+extract_devices(mos4("nfet_01v8_nvt"), { "SD" =&gt; NSD, "G" =&gt; HV5NA_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
+
+
+# Define connectivity for netlist extraction
+
+# Inter-layer
+connect(SUB,  PTAP)
+connect(NWELL,  NTAP)
+connect(LICON,   PTAP)
+connect(LICON,   NTAP)
+connect(PSD,    LICON)
+connect(NSD,    LICON)
+connect(POLY,   LICON)
+connect(LICON,   LI)
+connect(LI, MCON)
+connect(MCON,   MET1)
+connect(MET1,VIA1)
+connect(VIA1,   MET2)
+connect(MET2, VIA2)
+connect(VIA2,   MET3)
+connect(MET3, VIA3)
+connect(VIA3,   MET4)
+connect(MET4, VIA4)
+connect(VIA4,   MET5)
+# Attaching labels
+connect(SUB, SUBTXT)
+connect(SUB, SUBPIN)
+connect(NWELL, NWELLTXT)
+connect(POLY, POLYTXT)
+connect(LI, LITXT)
+connect(MET1, MET1TXT)
+connect(MET2, MET2TXT)
+connect(MET3, MET3TXT)
+connect(MET4, MET4TXT)
+connect(MET5, MET5TXT)
+
+# Global
+connect_global(SUB, "VNB")
+
+# Actually performs the extraction
+netlist # ... not really required
+
+# Flatten cells which are present in one netlist only
+align
+
+# Flat LVS: flatten all cells to transistor level.
+# This avoids hierarchical port identification issues where
+# KLayout misses output pins on cells whose LI shapes are
+# only on the PIN datatype (67/16) not DRAWING (67/20).
+netlist.flatten_circuit("*")
+schematic.flatten_circuit("*")
+
+netlist.make_top_level_pins
+netlist.combine_devices
+netlist.purge
+schematic.combine_devices
+schematic.purge
+
+# Tolerances for the devices extracted parameters
+#  tolerance(device_class_name, parameter_name [, :absolute =&gt; absolute_tolerance] [, :relative =&gt; relative_tolerance])
+tolerance("pfet_01v8", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("pfet_01v8", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("pfet_01v8_hvt", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("pfet_01v8_hvt", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("nfet_01v8", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("nfet_01v8", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("nfet_01v8_lvt", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("nfet_01v8_lvt", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+
+# NangateOpenCellLibrary Digital gates input equivalence :
+equivalent_pins("*AND2_1", "A", "B")
+equivalent_pins("*AND2_2", "A", "B")
+equivalent_pins("*AND2_4", "A", "B")
+equivalent_pins("*AND3_1", "A", "B", "C")
+equivalent_pins("*AND3_2", "A", "B", "C")
+equivalent_pins("*AND3_4", "A", "B", "C")
+equivalent_pins("*AND4_1", "A", "B", "C", "D")
+equivalent_pins("*AND4_2", "A", "B", "C", "D")
+equivalent_pins("*AND4_4", "A", "B", "C", "D")
+equivalent_pins("*NAND2_1", "A", "B")
+equivalent_pins("*NAND2_2", "A", "B")
+equivalent_pins("*NAND2_4", "A", "B")
+equivalent_pins("*NAND3_1", "A", "B", "C")
+equivalent_pins("*NAND3_2", "A", "B", "C")
+equivalent_pins("*NAND3_4", "A", "B", "C")
+equivalent_pins("*NAND4_X1", "A", "B", "C", "D")
+equivalent_pins("*NAND4_2", "A", "B", "C", "D")
+equivalent_pins("*NAND4_4", "A", "B", "C", "D")
+equivalent_pins("*OR2_1", "A", "B")
+equivalent_pins("*OR2_2", "A", "B")
+equivalent_pins("*OR2_4", "A", "B")
+equivalent_pins("*OR3_1", "A", "B", "C")
+equivalent_pins("*OR3_2", "A", "B", "C")
+equivalent_pins("*OR3_4", "A", "B", "C")
+equivalent_pins("*OR4_1", "A", "B", "C", "D")
+equivalent_pins("*OR4_2", "A", "B", "C", "D")
+equivalent_pins("*OR4_4", "A", "B", "C", "D")
+equivalent_pins("*NOR2_1", "A", "B")
+equivalent_pins("*NOR2_2", "A", "B")
+equivalent_pins("*NOR2_4", "A", "B")
+equivalent_pins("*NOR3_1", "A", "B", "C")
+equivalent_pins("*NOR3_2", "A", "B", "C")
+equivalent_pins("*NOR3_4", "A", "B", "C")
+equivalent_pins("*NOR4_1", "A", "B", "C", "D")
+equivalent_pins("*NOR4_2", "A", "B", "C", "D")
+equivalent_pins("*NOR4_4", "A", "B", "C", "D")
+equivalent_pins("*XOR2_1", "A", "B")
+equivalent_pins("*XOR2_2", "A", "B")
+equivalent_pins("*XNOR2_1", "A", "B")
+equivalent_pins("*XNOR2_2", "A", "B")
+
+#max_res(1000000)
+#min_caps(1e-15)
+
+if ! compare 
+  #raise "ERROR : Netlists don't match"
+  puts "ERROR : Netlists don't match"
+else
+  puts "INFO : Congratulations! Netlists match."
+end</text>
+</klayout-macro>

alu_w32_5ops_sky130_1000mhz/flow/lvs_reference.cdl.gz

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:6127d7f56a0a32dd07a76c6b1101ff31b9c973246c2a825d2cd71570bd0701c4
+size 29706

alu_w32_5ops_sky130_1000mhz/flow/lvs_report.lyrdb

@@ -0,0 +1,3116 @@
+#%lvsdb-klayout
+J(
+ W(alu_w32_5ops)
+ U(0.001)
+ L(l3 '64/20')
+ L(l29 '64/5')
+ L(l27)
+ L(l28 '64/59')
+ L(l4 '66/20')
+ L(l30)
+ L(l15 '66/44')
+ L(l16 '67/20')
+ L(l31 '67/5')
+ L(l17 '67/44')
+ L(l18 '68/20')
+ L(l32 '68/5')
+ L(l19 '68/44')
+ L(l20 '69/20')
+ L(l33 '69/5')
+ L(l21 '69/44')
+ L(l22 '70/20')
+ L(l34 '70/5')
+ L(l23 '70/44')
+ L(l24 '71/20')
+ L(l35)
+ L(l25 '71/44')
+ L(l26 '72/20')
+ L(l36 '72/5')
+ L(l9 '236/0')
+ L(l14)
+ L(l2)
+ L(l13)
+ L(l8)
+ C(l3 l3 l29 l14)
+ C(l29 l3 l29)
+ C(l27 l27 l9)
+ C(l28 l28 l9)
+ C(l4 l4 l30 l15)
+ C(l30 l4 l30)
+ C(l15 l4 l15 l16 l14 l2 l13 l8)
+ C(l16 l15 l16 l31 l17)
+ C(l31 l16 l31)
+ C(l17 l16 l17 l18)
+ C(l18 l17 l18 l32 l19)
+ C(l32 l18 l32)
+ C(l19 l18 l19 l20)
+ C(l20 l19 l20 l33 l21)
+ C(l33 l20 l33)
+ C(l21 l20 l21 l22)
+ C(l22 l21 l22 l34 l23)
+ C(l34 l22 l34)
+ C(l23 l22 l23 l24)
+ C(l24 l23 l24 l35 l25)
+ C(l35 l24 l35)
+ C(l25 l24 l25 l26)
+ C(l26 l25 l26 l36)
+ C(l36 l26 l36)
+ C(l9 l27 l28 l9 l13)
+ C(l14 l3 l15 l14)
+ C(l2 l15 l2)
+ C(l13 l15 l9 l13)
+ C(l8 l15 l8)
+ G(l9 VNB)
+ K(pfet_01v8 MOS4)
+ K(pfet_01v8_hvt MOS4)
+ K(pfet_g5v0d10v5 MOS4)
+ K(nfet_01v8 MOS4)
+ K(nfet_01v8_lvt MOS4)
+ K(nfet_g5v0d10v5 MOS4)
+ K(nfet_01v8_nvt MOS4)
+ D(D$pfet_01v8_hvt pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l2 (75 -210) (0 420) (75 0) (0 580) (260 0) (0 -1000))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$1 pfet_01v8_hvt
+  T(S
+   Q(l2 (-410 -500) (0 420) (75 0) (0 580) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$2 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (265 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$3 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (300 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$4 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$5 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$6 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$7 pfet_01v8_hvt
+  T(S
+   R(l2 (-340 -320) (265 640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (240 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$8 pfet_01v8_hvt
+  T(S
+   R(l2 (-315 -320) (240 640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (280 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$9 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -320) (280 640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (285 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$10 pfet_01v8_hvt
+  T(S
+   R(l2 (-340 -500) (265 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$11 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (295 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$12 pfet_01v8_hvt
+  T(S
+   R(l2 (-370 -500) (295 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (265 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$13 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l2 (75 -210) (0 420) (130 0) (0 580) (260 0) (0 -1000))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$14 pfet_01v8_hvt
+  T(S
+   Q(l2 (-465 -500) (0 420) (130 0) (0 580) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$15 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -500) (210 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$16 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (225 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$17 pfet_01v8_hvt
+  T(S
+   R(l2 (-300 -500) (225 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (465 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$18 pfet_01v8_hvt
+  T(S
+   R(l2 (-540 -500) (465 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$19 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -500) (210 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$20 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (330 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$21 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$22 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (210 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$23 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (270 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$24 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (210 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$25 pfet_01v8_hvt
+  T(S
+   Q(l2 (165 -430) (0 220) (-90 0) (0 420) (130 0) (0 360) (435 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-285 -210) (210 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$26 pfet_01v8_hvt
+  T(S
+   Q(l2 (-550 -500) (0 220) (-90 0) (0 420) (130 0) (0 360) (435 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (365 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$27 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$28 pfet_01v8_hvt
+  T(S
+   R(l2 (-375 -500) (300 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$29 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (730 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$30 pfet_01v8_hvt
+  T(S
+   R(l2 (-805 -500) (730 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$31 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -500) (210 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (330 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$32 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (360 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$33 pfet_01v8_hvt
+  T(S
+   R(l2 (-340 -500) (265 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$34 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -500) (210 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (390 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$35 pfet_01v8_hvt
+  T(S
+   R(l2 (-465 -500) (390 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (390 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$36 pfet_01v8_hvt
+  T(S
+   R(l2 (-465 -500) (390 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (635 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$37 pfet_01v8_hvt
+  T(S
+   R(l2 (-340 -210) (265 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (290 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$38 pfet_01v8_hvt
+  T(S
+   Q(l2 (205 -430) (0 220) (-130 0) (0 420) (620 0) (0 -640))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-365 -210) (290 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$39 pfet_01v8_hvt
+  T(S
+   Q(l2 (-565 -320) (0 220) (-130 0) (0 420) (620 0) (0 -640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (265 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$40 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (745 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$41 pfet_01v8_hvt
+  T(S
+   R(l2 (-820 -500) (745 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (235 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$42 pfet_01v8_hvt
+  T(S
+   R(l2 (-310 -500) (235 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (470 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$43 pfet_01v8_hvt
+  T(S
+   R(l2 (-545 -500) (470 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$44 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l2 (75 -210) (0 420) (75 0) (0 580) (260 0) (0 -1000))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$45 pfet_01v8_hvt
+  T(S
+   Q(l2 (-410 -500) (0 420) (75 0) (0 580) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (340 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$46 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (330 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$47 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -210) (330 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (210 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$48 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (330 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$49 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -210) (330 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l2 (75 -210) (0 420) (75 0) (0 580) (265 0) (0 -1000))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$50 pfet_01v8_hvt
+  T(S
+   Q(l2 (-415 -500) (0 420) (75 0) (0 580) (265 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$51 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$52 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (290 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$53 pfet_01v8_hvt
+  T(S
+   R(l2 (-365 -500) (290 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$54 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$55 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$56 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (265 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$57 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (305 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$58 pfet_01v8_hvt
+  T(S
+   R(l2 (-380 -500) (305 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (325 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$59 pfet_01v8_hvt
+  T(S
+   R(l2 (-400 -500) (325 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$60 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -210) (280 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (270 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$61 pfet_01v8_hvt
+  T(S
+   Q(l2 (155 -580) (0 370) (-80 0) (0 420) (130 0) (0 210) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-345 -210) (270 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$62 pfet_01v8_hvt
+  T(S
+   Q(l2 (-385 -500) (0 370) (-80 0) (0 420) (130 0) (0 210) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (475 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$63 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -320) (280 640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (270 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$64 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -320) (270 640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (270 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$65 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -320) (270 640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (450 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$66 pfet_01v8_hvt
+  T(S
+   R(l2 (-525 -320) (450 640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (370 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$67 pfet_01v8_hvt
+  T(S
+   R(l2 (-445 -320) (370 640))
+  )
+  T(G
+   R(l4 (-75 -320) (150 640))
+  )
+  T(D
+   R(l2 (75 -320) (310 640))
+  )
+  T(B
+   R(l3 (-75 -320) (150 640))
+  )
+ )
+ D(D$pfet_01v8_hvt$68 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (490 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$69 pfet_01v8_hvt
+  T(S
+   R(l2 (-565 -500) (490 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$70 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (785 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$71 pfet_01v8_hvt
+  T(S
+   R(l2 (-860 -500) (785 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (300 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$72 pfet_01v8_hvt
+  T(S
+   Q(l2 (-415 -500) (0 420) (75 0) (0 580) (265 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$73 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (270 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$74 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (315 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$75 pfet_01v8_hvt
+  T(S
+   Q(l2 (150 -225) (0 15) (-75 0) (0 420) (75 0) (0 270) (-10 0) (0 295) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-390 -210) (315 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$76 pfet_01v8_hvt
+  T(S
+   Q(l2 (-325 -500) (0 15) (-75 0) (0 420) (75 0) (0 270) (-10 0) (0 295) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$77 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (450 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$78 pfet_01v8_hvt
+  T(S
+   R(l2 (-525 -500) (450 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (370 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$79 pfet_01v8_hvt
+  T(S
+   R(l2 (-445 -500) (370 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (310 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$80 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$81 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (380 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$82 pfet_01v8_hvt
+  T(S
+   R(l2 (-455 -500) (380 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$83 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -420) (260 840))
+  )
+  T(G
+   R(l4 (-75 -420) (150 840))
+  )
+  T(D
+   R(l2 (75 -420) (270 840))
+  )
+  T(B
+   R(l3 (-75 -420) (150 840))
+  )
+ )
+ D(D$pfet_01v8_hvt$84 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -420) (270 840))
+  )
+  T(G
+   R(l4 (-75 -420) (150 840))
+  )
+  T(D
+   R(l2 (75 -420) (280 840))
+  )
+  T(B
+   R(l3 (-75 -420) (150 840))
+  )
+ )
+ D(D$pfet_01v8_hvt$85 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (310 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$86 pfet_01v8_hvt
+  T(S
+   R(l2 (-385 -500) (310 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (265 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$87 pfet_01v8_hvt
+  T(S
+   R(l2 (-340 -500) (265 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (345 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$88 pfet_01v8_hvt
+  T(S
+   R(l2 (-420 -500) (345 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (320 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$89 pfet_01v8_hvt
+  T(S
+   R(l2 (-395 -500) (320 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (330 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$90 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (330 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$91 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (320 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$92 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (275 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$93 pfet_01v8_hvt
+  T(S
+   R(l2 (-350 -500) (275 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$94 pfet_01v8_hvt
+  T(S
+   R(l2 (-410 -500) (335 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$95 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (390 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$96 pfet_01v8_hvt
+  T(S
+   R(l2 (-465 -500) (390 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (410 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$97 pfet_01v8_hvt
+  T(S
+   R(l2 (-485 -500) (410 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (290 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$98 pfet_01v8_hvt
+  T(S
+   R(l2 (-340 -500) (265 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (265 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$99 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$100 pfet_01v8_hvt
+  T(S
+   Q(l2 (150 -525) (0 315) (-75 0) (0 420) (75 0) (0 265) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-335 -210) (260 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$101 pfet_01v8_hvt
+  T(S
+   Q(l2 (-335 -500) (0 315) (-75 0) (0 420) (75 0) (0 265) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$102 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (355 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$103 pfet_01v8_hvt
+  T(S
+   R(l2 (-430 -500) (355 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$104 pfet_01v8_hvt
+  T(S
+   R(l2 (-355 -500) (280 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (285 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$105 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (380 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$106 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (625 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$107 pfet_01v8_hvt
+  T(S
+   R(l2 (-700 -500) (625 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (360 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$108 pfet_01v8_hvt
+  T(S
+   R(l2 (-435 -500) (360 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (420 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$109 pfet_01v8_hvt
+  T(S
+   R(l2 (-495 -500) (420 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (275 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$110 pfet_01v8_hvt
+  T(S
+   R(l2 (-350 -500) (275 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (300 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$111 pfet_01v8_hvt
+  T(S
+   R(l2 (-375 -500) (300 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$nfet_01v8 nfet_01v8
+  T(S
+   Q(l8 (150 -440) (0 230) (-75 0) (0 420) (335 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (-335 -210) (260 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$1 nfet_01v8
+  T(S
+   Q(l8 (-335 -325) (0 230) (-75 0) (0 420) (335 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$2 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$3 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$4 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$5 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (770 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$6 nfet_01v8
+  T(S
+   R(l8 (-845 -325) (770 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (320 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$7 nfet_01v8
+  T(S
+   R(l8 (-340 -210) (265 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (280 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$8 nfet_01v8
+  T(S
+   R(l8 (-355 -210) (280 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (280 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$9 nfet_01v8
+  T(S
+   R(l8 (-355 -210) (280 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (265 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$10 nfet_01v8
+  T(S
+   R(l8 (-340 -325) (265 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$11 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (295 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$12 nfet_01v8
+  T(S
+   R(l8 (-370 -325) (295 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (265 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$13 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l8 (75 -210) (0 420) (75 0) (0 230) (260 0) (0 -650))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$14 nfet_01v8
+  T(S
+   Q(l8 (-410 -325) (0 420) (75 0) (0 230) (260 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$15 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (285 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$16 nfet_01v8
+  T(S
+   R(l8 (-360 -325) (285 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (355 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$17 nfet_01v8
+  T(S
+   R(l8 (-430 -325) (355 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$18 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (330 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$19 nfet_01v8
+  T(S
+   R(l8 (-405 -325) (330 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$20 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (210 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$21 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$22 nfet_01v8
+  T(S
+   R(l8 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (210 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$23 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l8 (75 -210) (0 420) (315 0) (0 230) (250 0) (0 -650))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$24 nfet_01v8
+  T(S
+   Q(l8 (-640 -325) (0 420) (315 0) (0 230) (250 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (365 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$25 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (300 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$26 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (210 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$27 nfet_01v8
+  T(S
+   R(l8 (-285 -325) (210 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$28 nfet_01v8
+  T(S
+   R(l8 (-340 -325) (265 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (390 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$29 nfet_01v8
+  T(S
+   R(l8 (-465 -325) (390 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (390 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$30 nfet_01v8
+  T(S
+   R(l8 (-465 -325) (390 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (210 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$31 nfet_01v8
+  T(S
+   R(l8 (-285 -325) (210 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (605 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$32 nfet_01v8
+  T(S
+   R(l8 (-340 -210) (265 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (210 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$33 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (460 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$34 nfet_01v8
+  T(S
+   R(l8 (-535 -210) (460 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (265 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$35 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (350 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$36 nfet_01v8
+  T(S
+   R(l8 (-425 -325) (350 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$37 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$38 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$39 nfet_01v8
+  T(S
+   R(l8 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l8 (75 -210) (0 420) (75 0) (0 230) (260 0) (0 -650))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$40 nfet_01v8
+  T(S
+   Q(l8 (-410 -325) (0 420) (75 0) (0 230) (260 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$41 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (330 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$42 nfet_01v8
+  T(S
+   R(l8 (-405 -210) (330 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$43 nfet_01v8
+  T(S
+   R(l8 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$44 nfet_01v8
+  T(S
+   Q(l8 (150 -240) (0 30) (-75 0) (0 420) (75 0) (0 200) (265 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (-345 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$45 nfet_01v8
+  T(S
+   Q(l8 (-340 -325) (0 30) (-75 0) (0 420) (75 0) (0 200) (265 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$46 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$47 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$48 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (290 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$49 nfet_01v8
+  T(S
+   R(l8 (-365 -325) (290 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$50 nfet_01v8
+  T(S
+   R(l8 (-360 -325) (285 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$51 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$52 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (285 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$53 nfet_01v8
+  T(S
+   R(l8 (-285 -325) (210 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (365 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$54 nfet_01v8
+  T(S
+   R(l8 (-440 -325) (365 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (325 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$55 nfet_01v8
+  T(S
+   R(l8 (-400 -325) (325 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$56 nfet_01v8
+  T(S
+   R(l8 (-355 -210) (280 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$57 nfet_01v8
+  T(S
+   Q(l8 (205 -350) (0 140) (-130 0) (0 420) (130 0) (0 90) (260 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (-345 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$58 nfet_01v8
+  T(S
+   Q(l8 (-335 -325) (0 140) (-130 0) (0 420) (130 0) (0 90) (260 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$59 nfet_01v8
+  T(S
+   R(l8 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (610 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$60 nfet_01v8
+  T(S
+   R(l8 (-685 -210) (610 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (210 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$61 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (280 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$62 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (490 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$63 nfet_01v8
+  T(S
+   R(l8 (-565 -325) (490 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$64 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (610 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$65 nfet_01v8
+  T(S
+   R(l8 (-685 -325) (610 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (340 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$66 nfet_01v8
+  T(S
+   Q(l8 (-340 -325) (0 30) (-75 0) (0 420) (75 0) (0 200) (265 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$67 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (210 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$68 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l8 (75 -210) (0 420) (240 0) (0 230) (250 0) (0 -650))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$69 nfet_01v8
+  T(S
+   Q(l8 (-565 -325) (0 420) (240 0) (0 230) (250 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$70 nfet_01v8
+  T(S
+   R(l8 (-685 -325) (610 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (210 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$71 nfet_01v8
+  T(S
+   R(l8 (-285 -325) (210 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$72 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (365 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$73 nfet_01v8
+  T(S
+   R(l8 (-440 -325) (365 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (275 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$74 nfet_01v8
+  T(S
+   R(l8 (-350 -325) (275 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$75 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (265 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$76 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (285 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$77 nfet_01v8
+  T(S
+   R(l8 (-485 -325) (410 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$78 nfet_01v8
+  T(S
+   R(l8 (-355 -325) (280 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (310 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$79 nfet_01v8
+  T(S
+   R(l8 (-385 -325) (310 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (265 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$80 nfet_01v8
+  T(S
+   R(l8 (-340 -325) (265 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (345 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$81 nfet_01v8
+  T(S
+   R(l8 (-420 -325) (345 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (320 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$82 nfet_01v8
+  T(S
+   R(l8 (-395 -325) (320 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (330 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$83 nfet_01v8
+  T(S
+   R(l8 (-405 -325) (330 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (330 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$84 nfet_01v8
+  T(S
+   R(l8 (-405 -325) (330 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (320 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$85 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (790 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$86 nfet_01v8
+  T(S
+   R(l8 (-865 -325) (790 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (275 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$87 nfet_01v8
+  T(S
+   R(l8 (-350 -325) (275 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$88 nfet_01v8
+  T(S
+   R(l8 (-405 -325) (330 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (390 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$89 nfet_01v8
+  T(S
+   R(l8 (-465 -325) (390 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (410 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$90 nfet_01v8
+  T(S
+   R(l8 (-485 -325) (410 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (290 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$91 nfet_01v8
+  T(S
+   R(l8 (-340 -325) (265 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (800 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$92 nfet_01v8
+  T(S
+   R(l8 (-875 -325) (800 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$93 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (790 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$94 nfet_01v8
+  T(S
+   R(l8 (-865 -325) (790 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$95 nfet_01v8
+  T(S
+   R(l8 (-340 -325) (265 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (210 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$96 nfet_01v8
+  T(S
+   R(l8 (-285 -325) (210 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (425 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$97 nfet_01v8
+  T(S
+   R(l8 (-500 -325) (425 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (280 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$98 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (380 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$99 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (625 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$100 nfet_01v8
+  T(S
+   R(l8 (-700 -325) (625 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (360 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$101 nfet_01v8
+  T(S
+   R(l8 (-435 -325) (360 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (420 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$102 nfet_01v8
+  T(S
+   R(l8 (-495 -325) (420 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (365 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$103 nfet_01v8
+  T(S
+   R(l8 (-440 -325) (365 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (210 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$104 nfet_01v8
+  T(S
+   R(l8 (-285 -325) (210 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+)
+H(
+ K(NFET_01V8 MOS4)
+ K(PFET_01V8_HVT MOS4)
+ K(RES RES)
+)
+Z(
+)

alu_w32_5ops_sky130_1000mhz/flow/netlist.v

@@ -0,0 +1,2610 @@
+/* Generated by Yosys 0.46 (git sha1 e97731b9dda91fa5fa53ed87df7c34163ba59a41, clang++ 17.0.6 -fPIC -O3) */
+
+module alu_w32_5ops(a, b, sel, result);
+  wire _000_;
+  wire _001_;
+  wire _002_;
+  wire _003_;
+  wire _004_;
+  wire _005_;
+  wire _006_;
+  wire _007_;
+  wire _008_;
+  wire _009_;
+  wire _010_;
+  wire _011_;
+  wire _012_;
+  wire _013_;
+  wire _014_;
+  wire _015_;
+  wire _016_;
+  wire _017_;
+  wire _018_;
+  wire _019_;
+  wire _020_;
+  wire _021_;
+  wire _022_;
+  wire _023_;
+  wire _024_;
+  wire _025_;
+  wire _026_;
+  wire _027_;
+  wire _028_;
+  wire _029_;
+  wire _030_;
+  wire _031_;
+  wire _032_;
+  wire _033_;
+  wire _034_;
+  wire _035_;
+  wire _036_;
+  wire _037_;
+  wire _038_;
+  wire _039_;
+  wire _040_;
+  wire _041_;
+  wire _042_;
+  wire _043_;
+  wire _044_;
+  wire _045_;
+  wire _046_;
+  wire _047_;
+  wire _048_;
+  wire _049_;
+  wire _050_;
+  wire _051_;
+  wire _052_;
+  wire _053_;
+  wire _054_;
+  wire _055_;
+  wire _056_;
+  wire _057_;
+  wire _058_;
+  wire _059_;
+  wire _060_;
+  wire _061_;
+  wire _062_;
+  wire _063_;
+  wire _064_;
+  wire _065_;
+  wire _066_;
+  wire _067_;
+  wire _068_;
+  wire _069_;
+  wire _070_;
+  wire _071_;
+  wire _072_;
+  wire _073_;
+  wire _074_;
+  wire _075_;
+  wire _076_;
+  wire _077_;
+  wire _078_;
+  wire _079_;
+  wire _080_;
+  wire _081_;
+  wire _082_;
+  wire _083_;
+  wire _084_;
+  wire _085_;
+  wire _086_;
+  wire _087_;
+  wire _088_;
+  wire _089_;
+  wire _090_;
+  wire _091_;
+  wire _092_;
+  wire _093_;
+  wire _094_;
+  wire _095_;
+  wire _096_;
+  wire _097_;
+  wire _098_;
+  wire _099_;
+  wire _100_;
+  wire _101_;
+  wire _102_;
+  wire _103_;
+  wire _104_;
+  wire _105_;
+  wire _106_;
+  wire _107_;
+  wire _108_;
+  wire _109_;
+  wire _110_;
+  wire _111_;
+  wire _112_;
+  wire _113_;
+  wire _114_;
+  wire _115_;
+  wire _116_;
+  wire _117_;
+  wire _118_;
+  wire _119_;
+  wire _120_;
+  wire _121_;
+  wire _122_;
+  wire _123_;
+  wire _124_;
+  wire _125_;
+  wire _126_;
+  wire _127_;
+  wire _128_;
+  wire _129_;
+  wire _130_;
+  wire _131_;
+  wire _132_;
+  wire _133_;
+  wire _134_;
+  wire _135_;
+  wire _136_;
+  wire _137_;
+  wire _138_;
+  wire _139_;
+  wire _140_;
+  wire _141_;
+  wire _142_;
+  wire _143_;
+  wire _144_;
+  wire _145_;
+  wire _146_;
+  wire _147_;
+  wire _148_;
+  wire _149_;
+  wire _150_;
+  wire _151_;
+  wire _152_;
+  wire _153_;
+  wire _154_;
+  wire _155_;
+  wire _156_;
+  wire _157_;
+  wire _158_;
+  wire _159_;
+  wire _160_;
+  wire _161_;
+  wire _162_;
+  wire _163_;
+  wire _164_;
+  wire _165_;
+  wire _166_;
+  wire _167_;
+  wire _168_;
+  wire _169_;
+  wire _170_;
+  wire _171_;
+  wire _172_;
+  wire _173_;
+  wire _174_;
+  wire _175_;
+  wire _176_;
+  wire _177_;
+  wire _178_;
+  wire _179_;
+  wire _180_;
+  wire _181_;
+  wire _182_;
+  wire _183_;
+  wire _184_;
+  wire _185_;
+  wire _186_;
+  wire _187_;
+  wire _188_;
+  wire _189_;
+  wire _190_;
+  wire _191_;
+  wire _192_;
+  wire _193_;
+  wire _194_;
+  wire _195_;
+  wire _196_;
+  wire _197_;
+  wire _198_;
+  wire _199_;
+  wire _200_;
+  wire _201_;
+  wire _202_;
+  wire _203_;
+  wire _204_;
+  wire _205_;
+  wire _206_;
+  wire _207_;
+  wire _208_;
+  wire _209_;
+  wire _210_;
+  wire _211_;
+  wire _212_;
+  wire _213_;
+  wire _214_;
+  wire _215_;
+  wire _216_;
+  wire _217_;
+  wire _218_;
+  wire _219_;
+  wire _220_;
+  wire _221_;
+  wire _222_;
+  wire _223_;
+  wire _224_;
+  wire _225_;
+  wire _226_;
+  wire _227_;
+  wire _228_;
+  wire _229_;
+  wire _230_;
+  wire _231_;
+  wire _232_;
+  wire _233_;
+  wire _234_;
+  wire _235_;
+  wire _236_;
+  wire _237_;
+  wire _238_;
+  wire _239_;
+  wire _240_;
+  wire _241_;
+  wire _242_;
+  wire _243_;
+  wire _244_;
+  wire _245_;
+  wire _246_;
+  wire _247_;
+  wire _248_;
+  wire _249_;
+  wire _250_;
+  wire _251_;
+  wire _252_;
+  wire _253_;
+  wire _254_;
+  wire _255_;
+  wire _256_;
+  wire _257_;
+  wire _258_;
+  wire _259_;
+  wire _260_;
+  wire _261_;
+  wire _262_;
+  wire _263_;
+  wire _264_;
+  wire _265_;
+  wire _266_;
+  wire _267_;
+  wire _268_;
+  wire _269_;
+  wire _270_;
+  wire _271_;
+  wire _272_;
+  wire _273_;
+  wire _274_;
+  wire _275_;
+  wire _276_;
+  wire _277_;
+  wire _278_;
+  wire _279_;
+  wire _280_;
+  wire _281_;
+  wire _282_;
+  wire _283_;
+  wire _284_;
+  wire _285_;
+  wire _286_;
+  wire _287_;
+  wire _288_;
+  wire _289_;
+  wire _290_;
+  wire _291_;
+  wire _292_;
+  wire _293_;
+  wire _294_;
+  wire _295_;
+  wire _296_;
+  wire _297_;
+  wire _298_;
+  wire _299_;
+  wire _300_;
+  wire _301_;
+  wire _302_;
+  wire _303_;
+  wire _304_;
+  wire _305_;
+  wire _306_;
+  wire _307_;
+  wire _308_;
+  wire _309_;
+  wire _310_;
+  wire _311_;
+  wire _312_;
+  wire _313_;
+  wire _314_;
+  wire _315_;
+  wire _316_;
+  wire _317_;
+  wire _318_;
+  wire _319_;
+  wire _320_;
+  wire _321_;
+  wire _322_;
+  wire _323_;
+  wire _324_;
+  wire _325_;
+  wire _326_;
+  wire _327_;
+  wire _328_;
+  wire _329_;
+  wire _330_;
+  wire _331_;
+  wire _332_;
+  wire _333_;
+  wire _334_;
+  wire _335_;
+  wire _336_;
+  wire _337_;
+  wire _338_;
+  wire _339_;
+  wire _340_;
+  wire _341_;
+  wire _342_;
+  wire _343_;
+  wire _344_;
+  wire _345_;
+  wire _346_;
+  wire _347_;
+  wire _348_;
+  wire _349_;
+  wire _350_;
+  wire _351_;
+  wire _352_;
+  wire _353_;
+  wire _354_;
+  wire _355_;
+  wire _356_;
+  input [31:0] a;
+  wire [31:0] a;
+  input [31:0] b;
+  wire [31:0] b;
+  output [31:0] result;
+  wire [31:0] result;
+  input [2:0] sel;
+  wire [2:0] sel;
+  sky130_fd_sc_hd__clkinv_1 _357_ (
+    .A(a[28]),
+    .Y(_000_)
+  );
+  sky130_fd_sc_hd__nor2_1 _358_ (
+    .A(sel[0]),
+    .B(sel[1]),
+    .Y(_001_)
+  );
+  sky130_fd_sc_hd__nor3b_1 _359_ (
+    .A(sel[2]),
+    .B(sel[1]),
+    .C_N(sel[0]),
+    .Y(_002_)
+  );
+  sky130_fd_sc_hd__or3b_1 _360_ (
+    .A(sel[2]),
+    .B(sel[1]),
+    .C_N(sel[0]),
+    .X(_003_)
+  );
+  sky130_fd_sc_hd__nand2b_1 _361_ (
+    .A_N(a[0]),
+    .B(b[0]),
+    .Y(_004_)
+  );
+  sky130_fd_sc_hd__xor2_1 _362_ (
+    .A(b[0]),
+    .B(a[0]),
+    .X(_005_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _363_ (
+    .A1(_001_),
+    .A2(_002_),
+    .B1(_005_),
+    .Y(_006_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _364_ (
+    .A1(b[0]),
+    .A2(a[0]),
+    .B1(sel[0]),
+    .Y(_007_)
+  );
+  sky130_fd_sc_hd__lpflow_isobufsrc_1 _365_ (
+    .A(sel[1]),
+    .SLEEP(sel[2]),
+    .X(_008_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _366_ (
+    .A1(b[0]),
+    .A2(a[0]),
+    .B1(_008_),
+    .Y(_009_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _367_ (
+    .A1(_007_),
+    .A2(_009_),
+    .B1(_006_),
+    .Y(result[0])
+  );
+  sky130_fd_sc_hd__nand2_1 _368_ (
+    .A(b[0]),
+    .B(_003_),
+    .Y(_010_)
+  );
+  sky130_fd_sc_hd__xor2_1 _369_ (
+    .A(b[1]),
+    .B(_010_),
+    .X(_011_)
+  );
+  sky130_fd_sc_hd__xor2_1 _370_ (
+    .A(a[1]),
+    .B(_011_),
+    .X(_012_)
+  );
+  sky130_fd_sc_hd__nor2_1 _371_ (
+    .A(sel[2]),
+    .B(sel[1]),
+    .Y(_013_)
+  );
+  sky130_fd_sc_hd__lpflow_inputiso1p_1 _372_ (
+    .A(sel[2]),
+    .SLEEP(sel[1]),
+    .X(_014_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _373_ (
+    .A1(_004_),
+    .A2(_012_),
+    .B1(_014_),
+    .Y(_015_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _374_ (
+    .A1(_004_),
+    .A2(_012_),
+    .B1(_015_),
+    .Y(_016_)
+  );
+  sky130_fd_sc_hd__and2_0 _375_ (
+    .A(sel[0]),
+    .B(_008_),
+    .X(_017_)
+  );
+  sky130_fd_sc_hd__nand2_1 _376_ (
+    .A(sel[2]),
+    .B(_001_),
+    .Y(_018_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _377_ (
+    .A1(b[1]),
+    .A2(a[1]),
+    .B1(_018_),
+    .Y(_019_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _378_ (
+    .A1(b[1]),
+    .A2(a[1]),
+    .B1(_017_),
+    .B2(_019_),
+    .Y(_020_)
+  );
+  sky130_fd_sc_hd__lpflow_isobufsrc_1 _379_ (
+    .A(_008_),
+    .SLEEP(sel[0]),
+    .X(_021_)
+  );
+  sky130_fd_sc_hd__nand3_1 _380_ (
+    .A(b[1]),
+    .B(a[1]),
+    .C(_021_),
+    .Y(_022_)
+  );
+  sky130_fd_sc_hd__nand3_1 _381_ (
+    .A(_016_),
+    .B(_020_),
+    .C(_022_),
+    .Y(result[1])
+  );
+  sky130_fd_sc_hd__maj3_1 _382_ (
+    .A(a[1]),
+    .B(_004_),
+    .C(_011_),
+    .X(_023_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _383_ (
+    .A1(b[1]),
+    .A2(b[0]),
+    .B1(_003_),
+    .Y(_024_)
+  );
+  sky130_fd_sc_hd__xor2_1 _384_ (
+    .A(b[2]),
+    .B(_024_),
+    .X(_025_)
+  );
+  sky130_fd_sc_hd__xor2_1 _385_ (
+    .A(a[2]),
+    .B(_025_),
+    .X(_026_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _386_ (
+    .A1(_023_),
+    .A2(_026_),
+    .B1(_014_),
+    .Y(_027_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _387_ (
+    .A1(_023_),
+    .A2(_026_),
+    .B1(_027_),
+    .Y(_028_)
+  );
+  sky130_fd_sc_hd__nand3_1 _388_ (
+    .A(b[2]),
+    .B(a[2]),
+    .C(_021_),
+    .Y(_029_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _389_ (
+    .A1(b[2]),
+    .A2(a[2]),
+    .B1(_018_),
+    .Y(_030_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _390_ (
+    .A1(b[2]),
+    .A2(a[2]),
+    .B1(_017_),
+    .B2(_030_),
+    .Y(_031_)
+  );
+  sky130_fd_sc_hd__nand3_1 _391_ (
+    .A(_028_),
+    .B(_029_),
+    .C(_031_),
+    .Y(result[2])
+  );
+  sky130_fd_sc_hd__maj3_1 _392_ (
+    .A(a[2]),
+    .B(_023_),
+    .C(_025_),
+    .X(_032_)
+  );
+  sky130_fd_sc_hd__o31ai_1 _393_ (
+    .A1(b[1]),
+    .A2(b[2]),
+    .A3(b[0]),
+    .B1(_003_),
+    .Y(_033_)
+  );
+  sky130_fd_sc_hd__xor2_1 _394_ (
+    .A(b[3]),
+    .B(_033_),
+    .X(_034_)
+  );
+  sky130_fd_sc_hd__xor2_1 _395_ (
+    .A(a[3]),
+    .B(_034_),
+    .X(_035_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _396_ (
+    .A1(_032_),
+    .A2(_035_),
+    .B1(_014_),
+    .Y(_036_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _397_ (
+    .A1(_032_),
+    .A2(_035_),
+    .B1(_036_),
+    .Y(_037_)
+  );
+  sky130_fd_sc_hd__nand3_1 _398_ (
+    .A(b[3]),
+    .B(a[3]),
+    .C(_021_),
+    .Y(_038_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _399_ (
+    .A1(b[3]),
+    .A2(a[3]),
+    .B1(_018_),
+    .Y(_039_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _400_ (
+    .A1(b[3]),
+    .A2(a[3]),
+    .B1(_017_),
+    .B2(_039_),
+    .Y(_040_)
+  );
+  sky130_fd_sc_hd__nand3_1 _401_ (
+    .A(_037_),
+    .B(_038_),
+    .C(_040_),
+    .Y(result[3])
+  );
+  sky130_fd_sc_hd__maj3_1 _402_ (
+    .A(a[3]),
+    .B(_032_),
+    .C(_034_),
+    .X(_041_)
+  );
+  sky130_fd_sc_hd__or4_1 _403_ (
+    .A(b[1]),
+    .B(b[2]),
+    .C(b[3]),
+    .D(b[0]),
+    .X(_042_)
+  );
+  sky130_fd_sc_hd__nand2_1 _404_ (
+    .A(_003_),
+    .B(_042_),
+    .Y(_043_)
+  );
+  sky130_fd_sc_hd__xor2_1 _405_ (
+    .A(b[4]),
+    .B(_043_),
+    .X(_044_)
+  );
+  sky130_fd_sc_hd__xor2_1 _406_ (
+    .A(a[4]),
+    .B(_044_),
+    .X(_045_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _407_ (
+    .A1(_041_),
+    .A2(_045_),
+    .B1(_014_),
+    .Y(_046_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _408_ (
+    .A1(_041_),
+    .A2(_045_),
+    .B1(_046_),
+    .Y(_047_)
+  );
+  sky130_fd_sc_hd__nand3_1 _409_ (
+    .A(b[4]),
+    .B(a[4]),
+    .C(_021_),
+    .Y(_048_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _410_ (
+    .A1(b[4]),
+    .A2(a[4]),
+    .B1(_018_),
+    .Y(_049_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _411_ (
+    .A1(b[4]),
+    .A2(a[4]),
+    .B1(_017_),
+    .B2(_049_),
+    .Y(_050_)
+  );
+  sky130_fd_sc_hd__nand3_1 _412_ (
+    .A(_047_),
+    .B(_048_),
+    .C(_050_),
+    .Y(result[4])
+  );
+  sky130_fd_sc_hd__maj3_1 _413_ (
+    .A(a[4]),
+    .B(_041_),
+    .C(_044_),
+    .X(_051_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _414_ (
+    .A1(b[4]),
+    .A2(_042_),
+    .B1(_003_),
+    .Y(_052_)
+  );
+  sky130_fd_sc_hd__xor2_1 _415_ (
+    .A(b[5]),
+    .B(_052_),
+    .X(_053_)
+  );
+  sky130_fd_sc_hd__xor2_1 _416_ (
+    .A(a[5]),
+    .B(_053_),
+    .X(_054_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _417_ (
+    .A1(_051_),
+    .A2(_054_),
+    .B1(_014_),
+    .Y(_055_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _418_ (
+    .A1(_051_),
+    .A2(_054_),
+    .B1(_055_),
+    .Y(_056_)
+  );
+  sky130_fd_sc_hd__nand3_1 _419_ (
+    .A(b[5]),
+    .B(a[5]),
+    .C(_021_),
+    .Y(_057_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _420_ (
+    .A1(b[5]),
+    .A2(a[5]),
+    .B1(_018_),
+    .Y(_058_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _421_ (
+    .A1(b[5]),
+    .A2(a[5]),
+    .B1(_017_),
+    .B2(_058_),
+    .Y(_059_)
+  );
+  sky130_fd_sc_hd__nand3_1 _422_ (
+    .A(_056_),
+    .B(_057_),
+    .C(_059_),
+    .Y(result[5])
+  );
+  sky130_fd_sc_hd__maj3_1 _423_ (
+    .A(a[5]),
+    .B(_051_),
+    .C(_053_),
+    .X(_060_)
+  );
+  sky130_fd_sc_hd__o31ai_1 _424_ (
+    .A1(b[4]),
+    .A2(b[5]),
+    .A3(_042_),
+    .B1(_003_),
+    .Y(_061_)
+  );
+  sky130_fd_sc_hd__xor2_1 _425_ (
+    .A(b[6]),
+    .B(_061_),
+    .X(_062_)
+  );
+  sky130_fd_sc_hd__xor2_1 _426_ (
+    .A(a[6]),
+    .B(_062_),
+    .X(_063_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _427_ (
+    .A1(_060_),
+    .A2(_063_),
+    .B1(_014_),
+    .Y(_064_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _428_ (
+    .A1(_060_),
+    .A2(_063_),
+    .B1(_064_),
+    .Y(_065_)
+  );
+  sky130_fd_sc_hd__nand3_1 _429_ (
+    .A(b[6]),
+    .B(a[6]),
+    .C(_021_),
+    .Y(_066_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _430_ (
+    .A1(b[6]),
+    .A2(a[6]),
+    .B1(_018_),
+    .Y(_067_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _431_ (
+    .A1(b[6]),
+    .A2(a[6]),
+    .B1(_017_),
+    .B2(_067_),
+    .Y(_068_)
+  );
+  sky130_fd_sc_hd__nand3_1 _432_ (
+    .A(_065_),
+    .B(_066_),
+    .C(_068_),
+    .Y(result[6])
+  );
+  sky130_fd_sc_hd__maj3_1 _433_ (
+    .A(a[6]),
+    .B(_060_),
+    .C(_062_),
+    .X(_069_)
+  );
+  sky130_fd_sc_hd__nor4_1 _434_ (
+    .A(b[4]),
+    .B(b[5]),
+    .C(b[6]),
+    .D(_042_),
+    .Y(_070_)
+  );
+  sky130_fd_sc_hd__nor2_1 _435_ (
+    .A(_002_),
+    .B(_070_),
+    .Y(_071_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _436_ (
+    .A(b[7]),
+    .B(_071_),
+    .Y(_072_)
+  );
+  sky130_fd_sc_hd__xor2_1 _437_ (
+    .A(a[7]),
+    .B(_072_),
+    .X(_073_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _438_ (
+    .A1(_069_),
+    .A2(_073_),
+    .B1(_014_),
+    .Y(_074_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _439_ (
+    .A1(_069_),
+    .A2(_073_),
+    .B1(_074_),
+    .Y(_075_)
+  );
+  sky130_fd_sc_hd__nand3_1 _440_ (
+    .A(b[7]),
+    .B(a[7]),
+    .C(_021_),
+    .Y(_076_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _441_ (
+    .A1(b[7]),
+    .A2(a[7]),
+    .B1(_018_),
+    .Y(_077_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _442_ (
+    .A1(b[7]),
+    .A2(a[7]),
+    .B1(_017_),
+    .B2(_077_),
+    .Y(_078_)
+  );
+  sky130_fd_sc_hd__nand3_1 _443_ (
+    .A(_075_),
+    .B(_076_),
+    .C(_078_),
+    .Y(result[7])
+  );
+  sky130_fd_sc_hd__maj3_1 _444_ (
+    .A(a[7]),
+    .B(_069_),
+    .C(_072_),
+    .X(_079_)
+  );
+  sky130_fd_sc_hd__nand2b_1 _445_ (
+    .A_N(b[7]),
+    .B(_070_),
+    .Y(_080_)
+  );
+  sky130_fd_sc_hd__nand2_1 _446_ (
+    .A(_003_),
+    .B(_080_),
+    .Y(_081_)
+  );
+  sky130_fd_sc_hd__xor2_1 _447_ (
+    .A(b[8]),
+    .B(_081_),
+    .X(_082_)
+  );
+  sky130_fd_sc_hd__nand2_1 _448_ (
+    .A(a[8]),
+    .B(_082_),
+    .Y(_083_)
+  );
+  sky130_fd_sc_hd__clkinv_1 _449_ (
+    .A(_083_),
+    .Y(_084_)
+  );
+  sky130_fd_sc_hd__nor2_1 _450_ (
+    .A(a[8]),
+    .B(_082_),
+    .Y(_085_)
+  );
+  sky130_fd_sc_hd__nor2_1 _451_ (
+    .A(_084_),
+    .B(_085_),
+    .Y(_086_)
+  );
+  sky130_fd_sc_hd__nor2_1 _452_ (
+    .A(_079_),
+    .B(_086_),
+    .Y(_087_)
+  );
+  sky130_fd_sc_hd__nand2_1 _453_ (
+    .A(_079_),
+    .B(_086_),
+    .Y(_088_)
+  );
+  sky130_fd_sc_hd__nand2_1 _454_ (
+    .A(_013_),
+    .B(_088_),
+    .Y(_089_)
+  );
+  sky130_fd_sc_hd__nand3_1 _455_ (
+    .A(b[8]),
+    .B(a[8]),
+    .C(_021_),
+    .Y(_090_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _456_ (
+    .A1(b[8]),
+    .A2(a[8]),
+    .B1(_018_),
+    .Y(_091_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _457_ (
+    .A1(b[8]),
+    .A2(a[8]),
+    .B1(_017_),
+    .B2(_091_),
+    .Y(_092_)
+  );
+  sky130_fd_sc_hd__o211ai_1 _458_ (
+    .A1(_087_),
+    .A2(_089_),
+    .B1(_090_),
+    .C1(_092_),
+    .Y(result[8])
+  );
+  sky130_fd_sc_hd__nand2_1 _459_ (
+    .A(_083_),
+    .B(_088_),
+    .Y(_093_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _460_ (
+    .A1(b[8]),
+    .A2(_080_),
+    .B1(_003_),
+    .Y(_094_)
+  );
+  sky130_fd_sc_hd__xor2_1 _461_ (
+    .A(b[9]),
+    .B(_094_),
+    .X(_095_)
+  );
+  sky130_fd_sc_hd__and2_0 _462_ (
+    .A(a[9]),
+    .B(_095_),
+    .X(_096_)
+  );
+  sky130_fd_sc_hd__nor2_1 _463_ (
+    .A(a[9]),
+    .B(_095_),
+    .Y(_097_)
+  );
+  sky130_fd_sc_hd__nor2_1 _464_ (
+    .A(_096_),
+    .B(_097_),
+    .Y(_098_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _465_ (
+    .A1(_093_),
+    .A2(_098_),
+    .B1(_014_),
+    .Y(_099_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _466_ (
+    .A1(_093_),
+    .A2(_098_),
+    .B1(_099_),
+    .Y(_100_)
+  );
+  sky130_fd_sc_hd__nand3_1 _467_ (
+    .A(b[9]),
+    .B(a[9]),
+    .C(_021_),
+    .Y(_101_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _468_ (
+    .A1(b[9]),
+    .A2(a[9]),
+    .B1(_018_),
+    .Y(_102_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _469_ (
+    .A1(b[9]),
+    .A2(a[9]),
+    .B1(_017_),
+    .B2(_102_),
+    .Y(_103_)
+  );
+  sky130_fd_sc_hd__nand3_1 _470_ (
+    .A(_100_),
+    .B(_101_),
+    .C(_103_),
+    .Y(result[9])
+  );
+  sky130_fd_sc_hd__o31ai_1 _471_ (
+    .A1(b[8]),
+    .A2(b[9]),
+    .A3(_080_),
+    .B1(_003_),
+    .Y(_104_)
+  );
+  sky130_fd_sc_hd__xor2_1 _472_ (
+    .A(b[10]),
+    .B(_104_),
+    .X(_105_)
+  );
+  sky130_fd_sc_hd__nand2_1 _473_ (
+    .A(a[10]),
+    .B(_105_),
+    .Y(_106_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _474_ (
+    .A(a[10]),
+    .B(_105_),
+    .Y(_107_)
+  );
+  sky130_fd_sc_hd__a211oi_1 _475_ (
+    .A1(_079_),
+    .A2(_086_),
+    .B1(_096_),
+    .C1(_084_),
+    .Y(_108_)
+  );
+  sky130_fd_sc_hd__lpflow_inputiso1p_1 _476_ (
+    .A(_097_),
+    .SLEEP(_108_),
+    .X(_109_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _477_ (
+    .A1(_107_),
+    .A2(_109_),
+    .B1(_014_),
+    .Y(_110_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _478_ (
+    .A1(_107_),
+    .A2(_109_),
+    .B1(_110_),
+    .Y(_111_)
+  );
+  sky130_fd_sc_hd__nand3_1 _479_ (
+    .A(b[10]),
+    .B(a[10]),
+    .C(_021_),
+    .Y(_112_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _480_ (
+    .A1(b[10]),
+    .A2(a[10]),
+    .B1(_018_),
+    .Y(_113_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _481_ (
+    .A1(b[10]),
+    .A2(a[10]),
+    .B1(_017_),
+    .B2(_113_),
+    .Y(_114_)
+  );
+  sky130_fd_sc_hd__nand3_1 _482_ (
+    .A(_111_),
+    .B(_112_),
+    .C(_114_),
+    .Y(result[10])
+  );
+  sky130_fd_sc_hd__o31ai_1 _483_ (
+    .A1(_097_),
+    .A2(_107_),
+    .A3(_108_),
+    .B1(_106_),
+    .Y(_115_)
+  );
+  sky130_fd_sc_hd__or4_1 _484_ (
+    .A(b[8]),
+    .B(b[9]),
+    .C(b[10]),
+    .D(_080_),
+    .X(_116_)
+  );
+  sky130_fd_sc_hd__nand2_1 _485_ (
+    .A(_003_),
+    .B(_116_),
+    .Y(_117_)
+  );
+  sky130_fd_sc_hd__xor2_1 _486_ (
+    .A(b[11]),
+    .B(_117_),
+    .X(_118_)
+  );
+  sky130_fd_sc_hd__xor2_1 _487_ (
+    .A(a[11]),
+    .B(_118_),
+    .X(_119_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _488_ (
+    .A1(_115_),
+    .A2(_119_),
+    .B1(_014_),
+    .Y(_120_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _489_ (
+    .A1(_115_),
+    .A2(_119_),
+    .B1(_120_),
+    .Y(_121_)
+  );
+  sky130_fd_sc_hd__nand3_1 _490_ (
+    .A(b[11]),
+    .B(a[11]),
+    .C(_021_),
+    .Y(_122_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _491_ (
+    .A1(b[11]),
+    .A2(a[11]),
+    .B1(_018_),
+    .Y(_123_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _492_ (
+    .A1(b[11]),
+    .A2(a[11]),
+    .B1(_017_),
+    .B2(_123_),
+    .Y(_124_)
+  );
+  sky130_fd_sc_hd__nand3_1 _493_ (
+    .A(_121_),
+    .B(_122_),
+    .C(_124_),
+    .Y(result[11])
+  );
+  sky130_fd_sc_hd__maj3_1 _494_ (
+    .A(a[11]),
+    .B(_115_),
+    .C(_118_),
+    .X(_125_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _495_ (
+    .A1(b[11]),
+    .A2(_116_),
+    .B1(_003_),
+    .Y(_126_)
+  );
+  sky130_fd_sc_hd__xor2_1 _496_ (
+    .A(b[12]),
+    .B(_126_),
+    .X(_127_)
+  );
+  sky130_fd_sc_hd__and2_0 _497_ (
+    .A(a[12]),
+    .B(_127_),
+    .X(_128_)
+  );
+  sky130_fd_sc_hd__lpflow_inputiso1p_1 _498_ (
+    .A(a[12]),
+    .SLEEP(_127_),
+    .X(_129_)
+  );
+  sky130_fd_sc_hd__nand2b_1 _499_ (
+    .A_N(_128_),
+    .B(_129_),
+    .Y(_130_)
+  );
+  sky130_fd_sc_hd__nand2b_1 _500_ (
+    .A_N(_125_),
+    .B(_130_),
+    .Y(_131_)
+  );
+  sky130_fd_sc_hd__nand2b_1 _501_ (
+    .A_N(_130_),
+    .B(_125_),
+    .Y(_132_)
+  );
+  sky130_fd_sc_hd__nand3_1 _502_ (
+    .A(_013_),
+    .B(_131_),
+    .C(_132_),
+    .Y(_133_)
+  );
+  sky130_fd_sc_hd__nand3_1 _503_ (
+    .A(b[12]),
+    .B(a[12]),
+    .C(_021_),
+    .Y(_134_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _504_ (
+    .A1(b[12]),
+    .A2(a[12]),
+    .B1(_018_),
+    .Y(_135_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _505_ (
+    .A1(b[12]),
+    .A2(a[12]),
+    .B1(_017_),
+    .B2(_135_),
+    .Y(_136_)
+  );
+  sky130_fd_sc_hd__nand3_1 _506_ (
+    .A(_133_),
+    .B(_134_),
+    .C(_136_),
+    .Y(result[12])
+  );
+  sky130_fd_sc_hd__nand2b_1 _507_ (
+    .A_N(_128_),
+    .B(_132_),
+    .Y(_137_)
+  );
+  sky130_fd_sc_hd__nor3_1 _508_ (
+    .A(b[11]),
+    .B(b[12]),
+    .C(_116_),
+    .Y(_138_)
+  );
+  sky130_fd_sc_hd__nor2_1 _509_ (
+    .A(_002_),
+    .B(_138_),
+    .Y(_139_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _510_ (
+    .A(b[13]),
+    .B(_139_),
+    .Y(_140_)
+  );
+  sky130_fd_sc_hd__and2_0 _511_ (
+    .A(a[13]),
+    .B(_140_),
+    .X(_141_)
+  );
+  sky130_fd_sc_hd__nor2_1 _512_ (
+    .A(a[13]),
+    .B(_140_),
+    .Y(_142_)
+  );
+  sky130_fd_sc_hd__nor2_1 _513_ (
+    .A(_141_),
+    .B(_142_),
+    .Y(_143_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _514_ (
+    .A(_137_),
+    .B(_143_),
+    .Y(_144_)
+  );
+  sky130_fd_sc_hd__nand3_1 _515_ (
+    .A(b[13]),
+    .B(a[13]),
+    .C(_021_),
+    .Y(_145_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _516_ (
+    .A1(b[13]),
+    .A2(a[13]),
+    .B1(_018_),
+    .Y(_146_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _517_ (
+    .A1(b[13]),
+    .A2(a[13]),
+    .B1(_017_),
+    .B2(_146_),
+    .Y(_147_)
+  );
+  sky130_fd_sc_hd__o211ai_1 _518_ (
+    .A1(_014_),
+    .A2(_144_),
+    .B1(_145_),
+    .C1(_147_),
+    .Y(result[13])
+  );
+  sky130_fd_sc_hd__nand2b_1 _519_ (
+    .A_N(b[13]),
+    .B(_138_),
+    .Y(_148_)
+  );
+  sky130_fd_sc_hd__nand2_1 _520_ (
+    .A(_003_),
+    .B(_148_),
+    .Y(_149_)
+  );
+  sky130_fd_sc_hd__xor2_1 _521_ (
+    .A(b[14]),
+    .B(_149_),
+    .X(_150_)
+  );
+  sky130_fd_sc_hd__nand2_1 _522_ (
+    .A(a[14]),
+    .B(_150_),
+    .Y(_151_)
+  );
+  sky130_fd_sc_hd__xor2_1 _523_ (
+    .A(a[14]),
+    .B(_150_),
+    .X(_152_)
+  );
+  sky130_fd_sc_hd__clkinv_1 _524_ (
+    .A(_152_),
+    .Y(_153_)
+  );
+  sky130_fd_sc_hd__a211oi_1 _525_ (
+    .A1(_125_),
+    .A2(_129_),
+    .B1(_141_),
+    .C1(_128_),
+    .Y(_154_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _526_ (
+    .A1(_142_),
+    .A2(_154_),
+    .B1(_153_),
+    .Y(_155_)
+  );
+  sky130_fd_sc_hd__or3_1 _527_ (
+    .A(_142_),
+    .B(_153_),
+    .C(_154_),
+    .X(_156_)
+  );
+  sky130_fd_sc_hd__nand3_1 _528_ (
+    .A(_013_),
+    .B(_155_),
+    .C(_156_),
+    .Y(_157_)
+  );
+  sky130_fd_sc_hd__nand3_1 _529_ (
+    .A(b[14]),
+    .B(a[14]),
+    .C(_021_),
+    .Y(_158_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _530_ (
+    .A1(b[14]),
+    .A2(a[14]),
+    .B1(_018_),
+    .Y(_159_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _531_ (
+    .A1(b[14]),
+    .A2(a[14]),
+    .B1(_017_),
+    .B2(_159_),
+    .Y(_160_)
+  );
+  sky130_fd_sc_hd__nand3_1 _532_ (
+    .A(_157_),
+    .B(_158_),
+    .C(_160_),
+    .Y(result[14])
+  );
+  sky130_fd_sc_hd__nand2_1 _533_ (
+    .A(_151_),
+    .B(_156_),
+    .Y(_161_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _534_ (
+    .A1(b[14]),
+    .A2(_148_),
+    .B1(_003_),
+    .Y(_162_)
+  );
+  sky130_fd_sc_hd__xor2_1 _535_ (
+    .A(b[15]),
+    .B(_162_),
+    .X(_163_)
+  );
+  sky130_fd_sc_hd__and2_0 _536_ (
+    .A(a[15]),
+    .B(_163_),
+    .X(_164_)
+  );
+  sky130_fd_sc_hd__clkinv_1 _537_ (
+    .A(_164_),
+    .Y(_165_)
+  );
+  sky130_fd_sc_hd__lpflow_inputiso1p_1 _538_ (
+    .A(a[15]),
+    .SLEEP(_163_),
+    .X(_166_)
+  );
+  sky130_fd_sc_hd__nor2b_1 _539_ (
+    .A(_164_),
+    .B_N(_166_),
+    .Y(_167_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _540_ (
+    .A(_161_),
+    .B(_167_),
+    .Y(_168_)
+  );
+  sky130_fd_sc_hd__nand3_1 _541_ (
+    .A(b[15]),
+    .B(a[15]),
+    .C(_021_),
+    .Y(_169_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _542_ (
+    .A1(b[15]),
+    .A2(a[15]),
+    .B1(_018_),
+    .Y(_170_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _543_ (
+    .A1(b[15]),
+    .A2(a[15]),
+    .B1(_017_),
+    .B2(_170_),
+    .Y(_171_)
+  );
+  sky130_fd_sc_hd__o211ai_1 _544_ (
+    .A1(_014_),
+    .A2(_168_),
+    .B1(_169_),
+    .C1(_171_),
+    .Y(result[15])
+  );
+  sky130_fd_sc_hd__o31ai_1 _545_ (
+    .A1(b[14]),
+    .A2(b[15]),
+    .A3(_148_),
+    .B1(_003_),
+    .Y(_172_)
+  );
+  sky130_fd_sc_hd__xor2_1 _546_ (
+    .A(b[16]),
+    .B(_172_),
+    .X(_173_)
+  );
+  sky130_fd_sc_hd__nand2_1 _547_ (
+    .A(a[16]),
+    .B(_173_),
+    .Y(_174_)
+  );
+  sky130_fd_sc_hd__clkinv_1 _548_ (
+    .A(_174_),
+    .Y(_175_)
+  );
+  sky130_fd_sc_hd__nor2_1 _549_ (
+    .A(a[16]),
+    .B(_173_),
+    .Y(_176_)
+  );
+  sky130_fd_sc_hd__nor2_1 _550_ (
+    .A(_175_),
+    .B(_176_),
+    .Y(_177_)
+  );
+  sky130_fd_sc_hd__o311ai_0 _551_ (
+    .A1(_142_),
+    .A2(_153_),
+    .A3(_154_),
+    .B1(_165_),
+    .C1(_151_),
+    .Y(_178_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _552_ (
+    .A1(_166_),
+    .A2(_178_),
+    .B1(_177_),
+    .Y(_179_)
+  );
+  sky130_fd_sc_hd__nand3_1 _553_ (
+    .A(_166_),
+    .B(_177_),
+    .C(_178_),
+    .Y(_180_)
+  );
+  sky130_fd_sc_hd__nand2_1 _554_ (
+    .A(_013_),
+    .B(_180_),
+    .Y(_181_)
+  );
+  sky130_fd_sc_hd__nand3_1 _555_ (
+    .A(b[16]),
+    .B(a[16]),
+    .C(_021_),
+    .Y(_182_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _556_ (
+    .A1(b[16]),
+    .A2(a[16]),
+    .B1(_018_),
+    .Y(_183_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _557_ (
+    .A1(b[16]),
+    .A2(a[16]),
+    .B1(_017_),
+    .B2(_183_),
+    .Y(_184_)
+  );
+  sky130_fd_sc_hd__o211ai_1 _558_ (
+    .A1(_179_),
+    .A2(_181_),
+    .B1(_182_),
+    .C1(_184_),
+    .Y(result[16])
+  );
+  sky130_fd_sc_hd__a31oi_1 _559_ (
+    .A1(_166_),
+    .A2(_177_),
+    .A3(_178_),
+    .B1(_175_),
+    .Y(_185_)
+  );
+  sky130_fd_sc_hd__or4_1 _560_ (
+    .A(b[14]),
+    .B(b[15]),
+    .C(b[16]),
+    .D(_148_),
+    .X(_186_)
+  );
+  sky130_fd_sc_hd__nand2_1 _561_ (
+    .A(_003_),
+    .B(_186_),
+    .Y(_187_)
+  );
+  sky130_fd_sc_hd__xor2_1 _562_ (
+    .A(b[17]),
+    .B(_187_),
+    .X(_188_)
+  );
+  sky130_fd_sc_hd__and2_0 _563_ (
+    .A(a[17]),
+    .B(_188_),
+    .X(_189_)
+  );
+  sky130_fd_sc_hd__nor2_1 _564_ (
+    .A(a[17]),
+    .B(_188_),
+    .Y(_190_)
+  );
+  sky130_fd_sc_hd__nor2_1 _565_ (
+    .A(_189_),
+    .B(_190_),
+    .Y(_191_)
+  );
+  sky130_fd_sc_hd__xor2_1 _566_ (
+    .A(_185_),
+    .B(_191_),
+    .X(_192_)
+  );
+  sky130_fd_sc_hd__nand3_1 _567_ (
+    .A(b[17]),
+    .B(a[17]),
+    .C(_021_),
+    .Y(_193_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _568_ (
+    .A1(b[17]),
+    .A2(a[17]),
+    .B1(_018_),
+    .Y(_194_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _569_ (
+    .A1(b[17]),
+    .A2(a[17]),
+    .B1(_017_),
+    .B2(_194_),
+    .Y(_195_)
+  );
+  sky130_fd_sc_hd__o211ai_1 _570_ (
+    .A1(_014_),
+    .A2(_192_),
+    .B1(_193_),
+    .C1(_195_),
+    .Y(result[17])
+  );
+  sky130_fd_sc_hd__o21ai_0 _571_ (
+    .A1(b[17]),
+    .A2(_186_),
+    .B1(_003_),
+    .Y(_196_)
+  );
+  sky130_fd_sc_hd__xor2_1 _572_ (
+    .A(b[18]),
+    .B(_196_),
+    .X(_197_)
+  );
+  sky130_fd_sc_hd__nand2_1 _573_ (
+    .A(a[18]),
+    .B(_197_),
+    .Y(_198_)
+  );
+  sky130_fd_sc_hd__nor2_1 _574_ (
+    .A(a[18]),
+    .B(_197_),
+    .Y(_199_)
+  );
+  sky130_fd_sc_hd__lpflow_isobufsrc_1 _575_ (
+    .A(_198_),
+    .SLEEP(_199_),
+    .X(_200_)
+  );
+  sky130_fd_sc_hd__a311oi_1 _576_ (
+    .A1(_166_),
+    .A2(_177_),
+    .A3(_178_),
+    .B1(_189_),
+    .C1(_175_),
+    .Y(_201_)
+  );
+  sky130_fd_sc_hd__nor2_1 _577_ (
+    .A(_185_),
+    .B(_190_),
+    .Y(_202_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _578_ (
+    .A1(_189_),
+    .A2(_202_),
+    .B1(_200_),
+    .Y(_203_)
+  );
+  sky130_fd_sc_hd__o311ai_0 _579_ (
+    .A1(_189_),
+    .A2(_200_),
+    .A3(_202_),
+    .B1(_203_),
+    .C1(_013_),
+    .Y(_204_)
+  );
+  sky130_fd_sc_hd__nand3_1 _580_ (
+    .A(b[18]),
+    .B(a[18]),
+    .C(_021_),
+    .Y(_205_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _581_ (
+    .A1(b[18]),
+    .A2(a[18]),
+    .B1(_018_),
+    .Y(_206_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _582_ (
+    .A1(b[18]),
+    .A2(a[18]),
+    .B1(_017_),
+    .B2(_206_),
+    .Y(_207_)
+  );
+  sky130_fd_sc_hd__nand3_1 _583_ (
+    .A(_204_),
+    .B(_205_),
+    .C(_207_),
+    .Y(result[18])
+  );
+  sky130_fd_sc_hd__nand2_1 _584_ (
+    .A(_198_),
+    .B(_203_),
+    .Y(_208_)
+  );
+  sky130_fd_sc_hd__nor3_1 _585_ (
+    .A(b[17]),
+    .B(b[18]),
+    .C(_186_),
+    .Y(_209_)
+  );
+  sky130_fd_sc_hd__nor2_1 _586_ (
+    .A(_002_),
+    .B(_209_),
+    .Y(_210_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _587_ (
+    .A(b[19]),
+    .B(_210_),
+    .Y(_211_)
+  );
+  sky130_fd_sc_hd__nand2_1 _588_ (
+    .A(a[19]),
+    .B(_211_),
+    .Y(_212_)
+  );
+  sky130_fd_sc_hd__lpflow_inputiso1p_1 _589_ (
+    .A(a[19]),
+    .SLEEP(_211_),
+    .X(_213_)
+  );
+  sky130_fd_sc_hd__nand2_1 _590_ (
+    .A(_212_),
+    .B(_213_),
+    .Y(_214_)
+  );
+  sky130_fd_sc_hd__xor2_1 _591_ (
+    .A(_208_),
+    .B(_214_),
+    .X(_215_)
+  );
+  sky130_fd_sc_hd__nand3_1 _592_ (
+    .A(b[19]),
+    .B(a[19]),
+    .C(_021_),
+    .Y(_216_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _593_ (
+    .A1(b[19]),
+    .A2(a[19]),
+    .B1(_018_),
+    .Y(_217_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _594_ (
+    .A1(b[19]),
+    .A2(a[19]),
+    .B1(_017_),
+    .B2(_217_),
+    .Y(_218_)
+  );
+  sky130_fd_sc_hd__o211ai_1 _595_ (
+    .A1(_014_),
+    .A2(_215_),
+    .B1(_216_),
+    .C1(_218_),
+    .Y(result[19])
+  );
+  sky130_fd_sc_hd__nand2b_1 _596_ (
+    .A_N(b[19]),
+    .B(_209_),
+    .Y(_219_)
+  );
+  sky130_fd_sc_hd__nand2_1 _597_ (
+    .A(_003_),
+    .B(_219_),
+    .Y(_220_)
+  );
+  sky130_fd_sc_hd__xor2_1 _598_ (
+    .A(b[20]),
+    .B(_220_),
+    .X(_221_)
+  );
+  sky130_fd_sc_hd__nand2_1 _599_ (
+    .A(a[20]),
+    .B(_221_),
+    .Y(_222_)
+  );
+  sky130_fd_sc_hd__clkinv_1 _600_ (
+    .A(_222_),
+    .Y(_223_)
+  );
+  sky130_fd_sc_hd__nor2_1 _601_ (
+    .A(a[20]),
+    .B(_221_),
+    .Y(_224_)
+  );
+  sky130_fd_sc_hd__nor2_1 _602_ (
+    .A(_223_),
+    .B(_224_),
+    .Y(_225_)
+  );
+  sky130_fd_sc_hd__o311ai_0 _603_ (
+    .A1(_190_),
+    .A2(_199_),
+    .A3(_201_),
+    .B1(_212_),
+    .C1(_198_),
+    .Y(_226_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _604_ (
+    .A1(_213_),
+    .A2(_226_),
+    .B1(_225_),
+    .Y(_227_)
+  );
+  sky130_fd_sc_hd__and3_1 _605_ (
+    .A(_213_),
+    .B(_225_),
+    .C(_226_),
+    .X(_228_)
+  );
+  sky130_fd_sc_hd__or3_1 _606_ (
+    .A(_014_),
+    .B(_227_),
+    .C(_228_),
+    .X(_229_)
+  );
+  sky130_fd_sc_hd__nand3_1 _607_ (
+    .A(b[20]),
+    .B(a[20]),
+    .C(_021_),
+    .Y(_230_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _608_ (
+    .A1(b[20]),
+    .A2(a[20]),
+    .B1(_018_),
+    .Y(_231_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _609_ (
+    .A1(b[20]),
+    .A2(a[20]),
+    .B1(_017_),
+    .B2(_231_),
+    .Y(_232_)
+  );
+  sky130_fd_sc_hd__nand3_1 _610_ (
+    .A(_229_),
+    .B(_230_),
+    .C(_232_),
+    .Y(result[20])
+  );
+  sky130_fd_sc_hd__nor2_1 _611_ (
+    .A(_223_),
+    .B(_228_),
+    .Y(_233_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _612_ (
+    .A1(b[20]),
+    .A2(_219_),
+    .B1(_003_),
+    .Y(_234_)
+  );
+  sky130_fd_sc_hd__xor2_1 _613_ (
+    .A(b[21]),
+    .B(_234_),
+    .X(_235_)
+  );
+  sky130_fd_sc_hd__and2_0 _614_ (
+    .A(a[21]),
+    .B(_235_),
+    .X(_236_)
+  );
+  sky130_fd_sc_hd__nor2_1 _615_ (
+    .A(a[21]),
+    .B(_235_),
+    .Y(_237_)
+  );
+  sky130_fd_sc_hd__nor2_1 _616_ (
+    .A(_236_),
+    .B(_237_),
+    .Y(_238_)
+  );
+  sky130_fd_sc_hd__xor2_1 _617_ (
+    .A(_233_),
+    .B(_238_),
+    .X(_239_)
+  );
+  sky130_fd_sc_hd__nand3_1 _618_ (
+    .A(b[21]),
+    .B(a[21]),
+    .C(_021_),
+    .Y(_240_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _619_ (
+    .A1(b[21]),
+    .A2(a[21]),
+    .B1(_018_),
+    .Y(_241_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _620_ (
+    .A1(b[21]),
+    .A2(a[21]),
+    .B1(_017_),
+    .B2(_241_),
+    .Y(_242_)
+  );
+  sky130_fd_sc_hd__o211ai_1 _621_ (
+    .A1(_014_),
+    .A2(_239_),
+    .B1(_240_),
+    .C1(_242_),
+    .Y(result[21])
+  );
+  sky130_fd_sc_hd__o31ai_1 _622_ (
+    .A1(b[20]),
+    .A2(b[21]),
+    .A3(_219_),
+    .B1(_003_),
+    .Y(_243_)
+  );
+  sky130_fd_sc_hd__xor2_1 _623_ (
+    .A(b[22]),
+    .B(_243_),
+    .X(_244_)
+  );
+  sky130_fd_sc_hd__nand2_1 _624_ (
+    .A(a[22]),
+    .B(_244_),
+    .Y(_245_)
+  );
+  sky130_fd_sc_hd__nor2_1 _625_ (
+    .A(a[22]),
+    .B(_244_),
+    .Y(_246_)
+  );
+  sky130_fd_sc_hd__lpflow_isobufsrc_1 _626_ (
+    .A(_245_),
+    .SLEEP(_246_),
+    .X(_247_)
+  );
+  sky130_fd_sc_hd__a311oi_1 _627_ (
+    .A1(_213_),
+    .A2(_225_),
+    .A3(_226_),
+    .B1(_236_),
+    .C1(_223_),
+    .Y(_248_)
+  );
+  sky130_fd_sc_hd__nor2_1 _628_ (
+    .A(_233_),
+    .B(_237_),
+    .Y(_249_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _629_ (
+    .A1(_236_),
+    .A2(_249_),
+    .B1(_247_),
+    .Y(_250_)
+  );
+  sky130_fd_sc_hd__o311ai_0 _630_ (
+    .A1(_236_),
+    .A2(_247_),
+    .A3(_249_),
+    .B1(_250_),
+    .C1(_013_),
+    .Y(_251_)
+  );
+  sky130_fd_sc_hd__nand3_1 _631_ (
+    .A(b[22]),
+    .B(a[22]),
+    .C(_021_),
+    .Y(_252_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _632_ (
+    .A1(b[22]),
+    .A2(a[22]),
+    .B1(_018_),
+    .Y(_253_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _633_ (
+    .A1(b[22]),
+    .A2(a[22]),
+    .B1(_017_),
+    .B2(_253_),
+    .Y(_254_)
+  );
+  sky130_fd_sc_hd__nand3_1 _634_ (
+    .A(_251_),
+    .B(_252_),
+    .C(_254_),
+    .Y(result[22])
+  );
+  sky130_fd_sc_hd__nand2_1 _635_ (
+    .A(_245_),
+    .B(_250_),
+    .Y(_255_)
+  );
+  sky130_fd_sc_hd__or4_1 _636_ (
+    .A(b[20]),
+    .B(b[21]),
+    .C(b[22]),
+    .D(_219_),
+    .X(_256_)
+  );
+  sky130_fd_sc_hd__nand2_1 _637_ (
+    .A(_003_),
+    .B(_256_),
+    .Y(_257_)
+  );
+  sky130_fd_sc_hd__xor2_1 _638_ (
+    .A(b[23]),
+    .B(_257_),
+    .X(_258_)
+  );
+  sky130_fd_sc_hd__nand2_1 _639_ (
+    .A(a[23]),
+    .B(_258_),
+    .Y(_259_)
+  );
+  sky130_fd_sc_hd__lpflow_inputiso1p_1 _640_ (
+    .A(a[23]),
+    .SLEEP(_258_),
+    .X(_260_)
+  );
+  sky130_fd_sc_hd__nand2_1 _641_ (
+    .A(_259_),
+    .B(_260_),
+    .Y(_261_)
+  );
+  sky130_fd_sc_hd__xor2_1 _642_ (
+    .A(_255_),
+    .B(_261_),
+    .X(_262_)
+  );
+  sky130_fd_sc_hd__nand3_1 _643_ (
+    .A(b[23]),
+    .B(a[23]),
+    .C(_021_),
+    .Y(_263_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _644_ (
+    .A1(b[23]),
+    .A2(a[23]),
+    .B1(_018_),
+    .Y(_264_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _645_ (
+    .A1(b[23]),
+    .A2(a[23]),
+    .B1(_017_),
+    .B2(_264_),
+    .Y(_265_)
+  );
+  sky130_fd_sc_hd__o211ai_1 _646_ (
+    .A1(_014_),
+    .A2(_262_),
+    .B1(_263_),
+    .C1(_265_),
+    .Y(result[23])
+  );
+  sky130_fd_sc_hd__o21ai_0 _647_ (
+    .A1(b[23]),
+    .A2(_256_),
+    .B1(_003_),
+    .Y(_266_)
+  );
+  sky130_fd_sc_hd__xor2_1 _648_ (
+    .A(b[24]),
+    .B(_266_),
+    .X(_267_)
+  );
+  sky130_fd_sc_hd__nand2_1 _649_ (
+    .A(a[24]),
+    .B(_267_),
+    .Y(_268_)
+  );
+  sky130_fd_sc_hd__clkinv_1 _650_ (
+    .A(_268_),
+    .Y(_269_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _651_ (
+    .A(a[24]),
+    .B(_267_),
+    .Y(_270_)
+  );
+  sky130_fd_sc_hd__clkinv_1 _652_ (
+    .A(_270_),
+    .Y(_271_)
+  );
+  sky130_fd_sc_hd__o311ai_0 _653_ (
+    .A1(_237_),
+    .A2(_246_),
+    .A3(_248_),
+    .B1(_259_),
+    .C1(_245_),
+    .Y(_272_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _654_ (
+    .A1(_260_),
+    .A2(_272_),
+    .B1(_271_),
+    .Y(_273_)
+  );
+  sky130_fd_sc_hd__nand3_1 _655_ (
+    .A(_260_),
+    .B(_271_),
+    .C(_272_),
+    .Y(_274_)
+  );
+  sky130_fd_sc_hd__nand2_1 _656_ (
+    .A(_013_),
+    .B(_274_),
+    .Y(_275_)
+  );
+  sky130_fd_sc_hd__nand3_1 _657_ (
+    .A(b[24]),
+    .B(a[24]),
+    .C(_021_),
+    .Y(_276_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _658_ (
+    .A1(b[24]),
+    .A2(a[24]),
+    .B1(_018_),
+    .Y(_277_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _659_ (
+    .A1(b[24]),
+    .A2(a[24]),
+    .B1(_017_),
+    .B2(_277_),
+    .Y(_278_)
+  );
+  sky130_fd_sc_hd__o211ai_1 _660_ (
+    .A1(_273_),
+    .A2(_275_),
+    .B1(_276_),
+    .C1(_278_),
+    .Y(result[24])
+  );
+  sky130_fd_sc_hd__a31oi_1 _661_ (
+    .A1(_260_),
+    .A2(_271_),
+    .A3(_272_),
+    .B1(_269_),
+    .Y(_279_)
+  );
+  sky130_fd_sc_hd__nor3_1 _662_ (
+    .A(b[23]),
+    .B(b[24]),
+    .C(_256_),
+    .Y(_280_)
+  );
+  sky130_fd_sc_hd__nor2_1 _663_ (
+    .A(_002_),
+    .B(_280_),
+    .Y(_281_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _664_ (
+    .A(b[25]),
+    .B(_281_),
+    .Y(_282_)
+  );
+  sky130_fd_sc_hd__and2_0 _665_ (
+    .A(a[25]),
+    .B(_282_),
+    .X(_283_)
+  );
+  sky130_fd_sc_hd__nor2_1 _666_ (
+    .A(a[25]),
+    .B(_282_),
+    .Y(_284_)
+  );
+  sky130_fd_sc_hd__nor2_1 _667_ (
+    .A(_283_),
+    .B(_284_),
+    .Y(_285_)
+  );
+  sky130_fd_sc_hd__xor2_1 _668_ (
+    .A(_279_),
+    .B(_285_),
+    .X(_286_)
+  );
+  sky130_fd_sc_hd__nand3_1 _669_ (
+    .A(b[25]),
+    .B(a[25]),
+    .C(_021_),
+    .Y(_287_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _670_ (
+    .A1(b[25]),
+    .A2(a[25]),
+    .B1(_018_),
+    .Y(_288_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _671_ (
+    .A1(b[25]),
+    .A2(a[25]),
+    .B1(_017_),
+    .B2(_288_),
+    .Y(_289_)
+  );
+  sky130_fd_sc_hd__o211ai_1 _672_ (
+    .A1(_014_),
+    .A2(_286_),
+    .B1(_287_),
+    .C1(_289_),
+    .Y(result[25])
+  );
+  sky130_fd_sc_hd__nand2b_1 _673_ (
+    .A_N(b[25]),
+    .B(_280_),
+    .Y(_290_)
+  );
+  sky130_fd_sc_hd__nand2_1 _674_ (
+    .A(_003_),
+    .B(_290_),
+    .Y(_291_)
+  );
+  sky130_fd_sc_hd__xor2_1 _675_ (
+    .A(b[26]),
+    .B(_291_),
+    .X(_292_)
+  );
+  sky130_fd_sc_hd__nand2_1 _676_ (
+    .A(a[26]),
+    .B(_292_),
+    .Y(_293_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _677_ (
+    .A(a[26]),
+    .B(_292_),
+    .Y(_294_)
+  );
+  sky130_fd_sc_hd__a311oi_1 _678_ (
+    .A1(_260_),
+    .A2(_271_),
+    .A3(_272_),
+    .B1(_283_),
+    .C1(_269_),
+    .Y(_295_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _679_ (
+    .A1(_284_),
+    .A2(_295_),
+    .B1(_294_),
+    .Y(_296_)
+  );
+  sky130_fd_sc_hd__nor3_1 _680_ (
+    .A(_284_),
+    .B(_294_),
+    .C(_295_),
+    .Y(_297_)
+  );
+  sky130_fd_sc_hd__nand2_1 _681_ (
+    .A(_013_),
+    .B(_296_),
+    .Y(_298_)
+  );
+  sky130_fd_sc_hd__nand3_1 _682_ (
+    .A(b[26]),
+    .B(a[26]),
+    .C(_021_),
+    .Y(_299_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _683_ (
+    .A1(b[26]),
+    .A2(a[26]),
+    .B1(_018_),
+    .Y(_300_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _684_ (
+    .A1(b[26]),
+    .A2(a[26]),
+    .B1(_017_),
+    .B2(_300_),
+    .Y(_301_)
+  );
+  sky130_fd_sc_hd__o211ai_1 _685_ (
+    .A1(_297_),
+    .A2(_298_),
+    .B1(_299_),
+    .C1(_301_),
+    .Y(result[26])
+  );
+  sky130_fd_sc_hd__o31ai_1 _686_ (
+    .A1(_284_),
+    .A2(_294_),
+    .A3(_295_),
+    .B1(_293_),
+    .Y(_302_)
+  );
+  sky130_fd_sc_hd__nor2_1 _687_ (
+    .A(b[26]),
+    .B(_290_),
+    .Y(_303_)
+  );
+  sky130_fd_sc_hd__nor2_1 _688_ (
+    .A(_002_),
+    .B(_303_),
+    .Y(_304_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _689_ (
+    .A(b[27]),
+    .B(_304_),
+    .Y(_305_)
+  );
+  sky130_fd_sc_hd__nand2_1 _690_ (
+    .A(a[27]),
+    .B(_305_),
+    .Y(_306_)
+  );
+  sky130_fd_sc_hd__nor2_1 _691_ (
+    .A(a[27]),
+    .B(_305_),
+    .Y(_307_)
+  );
+  sky130_fd_sc_hd__lpflow_isobufsrc_1 _692_ (
+    .A(_306_),
+    .SLEEP(_307_),
+    .X(_308_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _693_ (
+    .A1(_302_),
+    .A2(_308_),
+    .B1(_014_),
+    .Y(_309_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _694_ (
+    .A1(_302_),
+    .A2(_308_),
+    .B1(_309_),
+    .Y(_310_)
+  );
+  sky130_fd_sc_hd__nand3_1 _695_ (
+    .A(b[27]),
+    .B(a[27]),
+    .C(_021_),
+    .Y(_311_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _696_ (
+    .A1(b[27]),
+    .A2(a[27]),
+    .B1(_018_),
+    .Y(_312_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _697_ (
+    .A1(b[27]),
+    .A2(a[27]),
+    .B1(_017_),
+    .B2(_312_),
+    .Y(_313_)
+  );
+  sky130_fd_sc_hd__nand3_1 _698_ (
+    .A(_310_),
+    .B(_311_),
+    .C(_313_),
+    .Y(result[27])
+  );
+  sky130_fd_sc_hd__a21oi_1 _699_ (
+    .A1(b[27]),
+    .A2(_003_),
+    .B1(_304_),
+    .Y(_314_)
+  );
+  sky130_fd_sc_hd__nand2b_1 _700_ (
+    .A_N(b[28]),
+    .B(_314_),
+    .Y(_315_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _701_ (
+    .A(b[28]),
+    .B(_314_),
+    .Y(_316_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _702_ (
+    .A(_000_),
+    .B(_316_),
+    .Y(_317_)
+  );
+  sky130_fd_sc_hd__o311a_1 _703_ (
+    .A1(_284_),
+    .A2(_294_),
+    .A3(_295_),
+    .B1(_306_),
+    .C1(_293_),
+    .X(_318_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _704_ (
+    .A1(a[27]),
+    .A2(_305_),
+    .B1(_302_),
+    .Y(_319_)
+  );
+  sky130_fd_sc_hd__or3_1 _705_ (
+    .A(_307_),
+    .B(_317_),
+    .C(_318_),
+    .X(_320_)
+  );
+  sky130_fd_sc_hd__a31oi_1 _706_ (
+    .A1(_306_),
+    .A2(_317_),
+    .A3(_319_),
+    .B1(_014_),
+    .Y(_321_)
+  );
+  sky130_fd_sc_hd__nand3_1 _707_ (
+    .A(b[28]),
+    .B(a[28]),
+    .C(_021_),
+    .Y(_322_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _708_ (
+    .A1(b[28]),
+    .A2(a[28]),
+    .B1(_018_),
+    .Y(_323_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _709_ (
+    .A1(b[28]),
+    .A2(a[28]),
+    .B1(_017_),
+    .B2(_323_),
+    .Y(_324_)
+  );
+  sky130_fd_sc_hd__nand2_1 _710_ (
+    .A(_322_),
+    .B(_324_),
+    .Y(_325_)
+  );
+  sky130_fd_sc_hd__a21o_1 _711_ (
+    .A1(_320_),
+    .A2(_321_),
+    .B1(_325_),
+    .X(result[28])
+  );
+  sky130_fd_sc_hd__nand2_1 _712_ (
+    .A(_003_),
+    .B(_315_),
+    .Y(_326_)
+  );
+  sky130_fd_sc_hd__xor2_1 _713_ (
+    .A(b[29]),
+    .B(_326_),
+    .X(_327_)
+  );
+  sky130_fd_sc_hd__nand2_1 _714_ (
+    .A(a[29]),
+    .B(_327_),
+    .Y(_328_)
+  );
+  sky130_fd_sc_hd__o32a_1 _715_ (
+    .A1(_307_),
+    .A2(_317_),
+    .A3(_318_),
+    .B1(_316_),
+    .B2(_000_),
+    .X(_329_)
+  );
+  sky130_fd_sc_hd__nor2_1 _716_ (
+    .A(a[29]),
+    .B(_327_),
+    .Y(_330_)
+  );
+  sky130_fd_sc_hd__lpflow_isobufsrc_1 _717_ (
+    .A(_328_),
+    .SLEEP(_330_),
+    .X(_331_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _718_ (
+    .A(_329_),
+    .B(_331_),
+    .Y(_332_)
+  );
+  sky130_fd_sc_hd__nand2_1 _719_ (
+    .A(_013_),
+    .B(_332_),
+    .Y(_333_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _720_ (
+    .A1(b[29]),
+    .A2(a[29]),
+    .B1(_018_),
+    .Y(_334_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _721_ (
+    .A1(b[29]),
+    .A2(a[29]),
+    .B1(_017_),
+    .B2(_334_),
+    .Y(_335_)
+  );
+  sky130_fd_sc_hd__nand3_1 _722_ (
+    .A(b[29]),
+    .B(a[29]),
+    .C(_021_),
+    .Y(_336_)
+  );
+  sky130_fd_sc_hd__nand3_1 _723_ (
+    .A(_333_),
+    .B(_335_),
+    .C(_336_),
+    .Y(result[29])
+  );
+  sky130_fd_sc_hd__o21ai_0 _724_ (
+    .A1(b[29]),
+    .A2(_315_),
+    .B1(_003_),
+    .Y(_337_)
+  );
+  sky130_fd_sc_hd__xor2_1 _725_ (
+    .A(b[30]),
+    .B(_337_),
+    .X(_338_)
+  );
+  sky130_fd_sc_hd__nand2_1 _726_ (
+    .A(a[30]),
+    .B(_338_),
+    .Y(_339_)
+  );
+  sky130_fd_sc_hd__xor2_1 _727_ (
+    .A(a[30]),
+    .B(_338_),
+    .X(_340_)
+  );
+  sky130_fd_sc_hd__clkinv_1 _728_ (
+    .A(_340_),
+    .Y(_341_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _729_ (
+    .A1(_328_),
+    .A2(_329_),
+    .B1(_330_),
+    .Y(_342_)
+  );
+  sky130_fd_sc_hd__nor2_1 _730_ (
+    .A(_340_),
+    .B(_342_),
+    .Y(_343_)
+  );
+  sky130_fd_sc_hd__a211o_1 _731_ (
+    .A1(_328_),
+    .A2(_329_),
+    .B1(_330_),
+    .C1(_341_),
+    .X(_344_)
+  );
+  sky130_fd_sc_hd__nand2_1 _732_ (
+    .A(_013_),
+    .B(_344_),
+    .Y(_345_)
+  );
+  sky130_fd_sc_hd__nand3_1 _733_ (
+    .A(b[30]),
+    .B(a[30]),
+    .C(_021_),
+    .Y(_346_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _734_ (
+    .A1(b[30]),
+    .A2(a[30]),
+    .B1(_018_),
+    .Y(_347_)
+  );
+  sky130_fd_sc_hd__o22ai_1 _735_ (
+    .A1(b[30]),
+    .A2(a[30]),
+    .B1(_017_),
+    .B2(_347_),
+    .Y(_348_)
+  );
+  sky130_fd_sc_hd__o211ai_1 _736_ (
+    .A1(_343_),
+    .A2(_345_),
+    .B1(_346_),
+    .C1(_348_),
+    .Y(result[30])
+  );
+  sky130_fd_sc_hd__xnor2_1 _737_ (
+    .A(b[31]),
+    .B(a[31]),
+    .Y(_349_)
+  );
+  sky130_fd_sc_hd__o31ai_1 _738_ (
+    .A1(b[29]),
+    .A2(b[30]),
+    .A3(_315_),
+    .B1(_003_),
+    .Y(_350_)
+  );
+  sky130_fd_sc_hd__xor2_1 _739_ (
+    .A(_349_),
+    .B(_350_),
+    .X(_351_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _740_ (
+    .A1(_339_),
+    .A2(_344_),
+    .B1(_351_),
+    .Y(_352_)
+  );
+  sky130_fd_sc_hd__a31o_1 _741_ (
+    .A1(_339_),
+    .A2(_344_),
+    .A3(_351_),
+    .B1(_014_),
+    .X(_353_)
+  );
+  sky130_fd_sc_hd__a21oi_1 _742_ (
+    .A1(b[31]),
+    .A2(a[31]),
+    .B1(sel[0]),
+    .Y(_354_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _743_ (
+    .A1(b[31]),
+    .A2(a[31]),
+    .B1(_008_),
+    .Y(_355_)
+  );
+  sky130_fd_sc_hd__o22a_1 _744_ (
+    .A1(_018_),
+    .A2(_349_),
+    .B1(_354_),
+    .B2(_355_),
+    .X(_356_)
+  );
+  sky130_fd_sc_hd__o21ai_0 _745_ (
+    .A1(_352_),
+    .A2(_353_),
+    .B1(_356_),
+    .Y(result[31])
+  );
+endmodule

alu_w32_5ops_sky130_1000mhz/flow/output.def.gz

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:f9f29f7154fd35add8645484ba1be45a446c1d9efa5acf97fb9883f46a1e8a95
+size 61144

alu_w32_5ops_sky130_1000mhz/flow/write_cdl.tcl

@@ -0,0 +1,4 @@
+read_lef /nix/store/sjh17jnslbv9d60450qybp1ajym2fb83-source/flow/platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
+read_lef /nix/store/sjh17jnslbv9d60450qybp1ajym2fb83-source/flow/platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
+read_def /tmp/zyphar_pnr_959439.def
+write_cdl -masters /nix/store/sjh17jnslbv9d60450qybp1ajym2fb83-source/flow/platforms/sky130hd/cdl/sky130hd.cdl /tmp/datagen_output/alu_w32_5ops_sky130_1000mhz/flow/design_only.cdl

alu_w32_5ops_sky130_1000mhz/result.json

@@ -0,0 +1,43 @@
+{
+  "run_id": "alu_w32_5ops_sky130_1000mhz",
+  "design": "alu_w32_5ops",
+  "pdk": "sky130",
+  "frequency_mhz": 1000,
+  "status": "success",
+  "metadata": {
+    "type": "alu",
+    "width": 32,
+    "ops": [
+      "add",
+      "sub",
+      "and",
+      "or",
+      "xor"
+    ],
+    "sel_width": 3,
+    "combinational": true,
+    "name": "alu_w32_5ops",
+    "files": {
+      "design": "alu_w32_5ops.v",
+      "testbench": "alu_w32_5ops_tb.v"
+    }
+  },
+  "timings": {
+    "flow_total": 0.0,
+    "note": "reused_existing_flow",
+    "extraction": 0.3906853199005127
+  },
+  "errors": [],
+  "extracted": {
+    "geometry_patches": 64,
+    "physics_labels": 457,
+    "drc_labels": 1,
+    "pin_access": 101,
+    "cell_neighborhoods": 214,
+    "timing_contexts": 1,
+    "power_grid": 374,
+    "mesoscale_blocks": 16,
+    "trajectory_snapshots": 9,
+    "deepgate_aig": 1
+  }
+}

alu_w32_5ops_sky130_500mhz/flow/design_only.cdl.gz

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:4d112279e2289317cf88540e4a86a031b8b347597483848d5d476b4fc43decfb
+size 5735

alu_w32_5ops_sky130_500mhz/result.json

@@ -0,0 +1,43 @@
+{
+  "run_id": "alu_w32_5ops_sky130_500mhz",
+  "design": "alu_w32_5ops",
+  "pdk": "sky130",
+  "frequency_mhz": 500,
+  "status": "success",
+  "metadata": {
+    "type": "alu",
+    "width": 32,
+    "ops": [
+      "add",
+      "sub",
+      "and",
+      "or",
+      "xor"
+    ],
+    "sel_width": 3,
+    "combinational": true,
+    "name": "alu_w32_5ops",
+    "files": {
+      "design": "alu_w32_5ops.v",
+      "testbench": "alu_w32_5ops_tb.v"
+    }
+  },
+  "timings": {
+    "flow_total": 0.0,
+    "note": "reused_existing_flow",
+    "extraction": 0.39151597023010254
+  },
+  "errors": [],
+  "extracted": {
+    "geometry_patches": 64,
+    "physics_labels": 457,
+    "drc_labels": 1,
+    "pin_access": 101,
+    "cell_neighborhoods": 214,
+    "timing_contexts": 1,
+    "power_grid": 374,
+    "mesoscale_blocks": 16,
+    "trajectory_snapshots": 9,
+    "deepgate_aig": 1
+  }
+}

alu_w4_2ops_sky130_50mhz/flow/clean_gds_for_lvs.py

@@ -0,0 +1,52 @@
+import pya
+import sys
+
+layout = pya.Layout()
+layout.read("/tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/alu_w4_2ops.gds")
+
+top_cell = None
+for tc in layout.top_cells():
+    if tc.name == "alu_w4_2ops" or tc.name != "OUTLINE":
+        top_cell = tc
+        break
+
+if top_cell is None:
+    print("ERROR: No top cell found")
+    sys.exit(1)
+
+skip_patterns = ["sky130_fd_sc_hd__fill_", "sky130_fd_sc_hd__decap_", "sky130_fd_sc_hd__conb_"]
+
+removed = 0
+to_delete = []
+for inst in top_cell.each_inst():
+    cell_name = inst.cell.name
+    for pat in skip_patterns:
+        if pat in cell_name:
+            to_delete.append(inst)
+            break
+
+for inst in to_delete:
+    inst.delete()
+    removed += 1
+
+print("Removed %d non-logic cell instances" % removed)
+
+# Remove orphaned cell definitions
+used_cells = set()
+for cell in layout.each_cell():
+    for inst in cell.each_inst():
+        used_cells.add(inst.cell.cell_index())
+used_cells.add(top_cell.cell_index())
+
+orphans = []
+for cell in layout.each_cell():
+    if cell.cell_index() not in used_cells and cell.cell_index() != top_cell.cell_index():
+        orphans.append(cell.cell_index())
+
+for ci in orphans:
+    layout.delete_cell(ci)
+
+print("Removed %d orphaned cell definitions" % len(orphans))
+
+layout.write("/tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/lvs_cleaned.gds")
+print("Cleaned GDS written to /tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/lvs_cleaned.gds")

alu_w4_2ops_sky130_50mhz/flow/drc_deck_patched.lydrc

@@ -0,0 +1,918 @@
+<?xml version="1.0" encoding="utf-8"?>
+<klayout-macro>
+ <description/>
+ <version/>
+ <category>drc</category>
+ <prolog/>
+ <epilog/>
+ <doc/>
+ <autorun>false</autorun>
+ <autorun-early>false</autorun-early>
+ <shortcut/>
+ <show-in-menu>true</show-in-menu>
+ <group-name>drc_scripts</group-name>
+ <menu-path>tools_menu.drc.end</menu-path>
+ <interpreter>dsl</interpreter>
+ <dsl-interpreter-name>drc-dsl-xml</dsl-interpreter-name>
+ <text>#
+#  DRC  for  SKY130 according to :
+#   https://skywater-pdk.readthedocs.io/en/latest/rules/periphery.html
+#   https://skywater-pdk.readthedocs.io/en/latest/rules/layers.html
+#
+#   Distributed under GNU GPLv3: https://www.gnu.org/licenses/
+#
+#  History :
+#   2020-10-04 : v1.0 : initial release
+#
+##########################################################################################
+
+# optionnal for a batch launch :   klayout -b -rd in_gds=my_layout.gds -rd report_file=6_drc_count.rpt -r drc_sky130.drc
+if $in_gds
+  source($in_gds, $topcell)
+end
+
+if $report_file
+  report("SKY130 DRC runset", $report_file)
+else
+  report("SKY130 DRC runset", File.join(File.dirname(RBA::CellView::active.filename), "6_drc_count.rpt"))
+end
+
+AL = true  # do not change
+CU = false  # do not change
+# choose betwen only one of  AL  or  CU  back-end flow here :
+backend_flow = AL
+
+# enable / disable rule groups
+FEOL    = false # front-end-of-line checks
+BEOL    = true # back-end-of-line checks
+OFFGRID = true # manufacturing grid/angle checks
+
+# klayout setup
+########################
+# use a tile size of 1mm - not used in deep mode-
+tiles(1000.um)
+# use a tile border of 10 micron:
+tile_borders(1.um)
+#no_borders
+
+# hierachical
+deep
+
+# use 4 cpu cores
+threads(4)
+# if more inof is needed, set true
+verbose(true)
+
+# layers definitions
+########################
+
+# all except purpose (datatype) 5 -- label and 44 -- via
+li_wildcard = "67/0-4,6-43,45-*"
+mcon_wildcard = "67/44"
+
+m1_wildcard = "68/0-4,6-43,45-*"
+via_wildcard = "68/44"
+
+m2_wildcard = "69/0-4,6-43,45-*"
+via2_wildcard = "69/44"
+
+m3_wildcard = "70/0-4,6-43,45-*"
+via3_wildcard = "70/44"
+
+m4_wildcard = "71/0-4,6-43,45-*"
+via4_wildcard = "71/44"
+
+m5_wildcard = "72/0-4,6-43,45-*"
+
+diff = input(65, 20)
+tap = polygons(65, 44)
+nwell = polygons(64, 20)
+dnwell = polygons(64, 18)
+pwbm = polygons(19, 44)
+pwde = polygons(124, 20)
+natfet = polygons(124, 21)
+hvtr = polygons(18, 20)
+hvtp = polygons(78, 44)
+ldntm = polygons(11, 44)
+hvi = polygons(75, 20)
+tunm = polygons(80, 20)
+lvtn = polygons(125, 44)
+poly = polygons(66, 20)
+hvntm = polygons(125, 20)
+nsdm = polygons(93, 44)
+psdm = polygons(94, 20)
+rpm = polygons(86, 20)
+urpm = polygons(79, 20)
+npc = polygons(95, 20)
+licon = polygons(66, 44)
+
+li = polygons(li_wildcard)
+mcon = polygons(mcon_wildcard)
+
+m1 = polygons(m1_wildcard)
+via = polygons(via_wildcard)
+
+m2 = polygons(m2_wildcard)
+via2 = polygons(via2_wildcard)
+
+m3 = polygons(m3_wildcard)
+via3 = polygons(via3_wildcard)
+
+m4 = polygons(m4_wildcard)
+via4 = polygons(via4_wildcard)
+
+m5 = polygons(m5_wildcard)
+
+pad = polygons(76, 20)
+nsm = polygons(61, 20)
+capm = polygons(89, 44)
+cap2m = polygons(97, 44)
+vhvi = polygons(74, 21)
+uhvi = polygons(74, 22)
+npn = polygons(82, 20)
+inductor = polygons(82, 24)
+vpp = polygons(82, 64)
+pnp = polygons(82, 44)
+lvs_prune = polygons(84, 44)
+ncm = polygons(92, 44)
+padcenter = polygons(81, 20)
+mf = polygons(76, 44)
+areaid_sl = polygons(81, 1)
+areaid_ce = polygons(81, 2)
+areaid_fe = polygons(81, 3)
+areaid_sc = polygons(81, 4)
+areaid_sf = polygons(81, 6)
+areaid_sw = polygons(81, 7)
+areaid_sr = polygons(81, 8)
+areaid_mt = polygons(81, 10)
+areaid_dt = polygons(81, 11)
+areaid_ft = polygons(81, 12)
+areaid_ww = polygons(81, 13)
+areaid_ld = polygons(81, 14)
+areaid_ns = polygons(81, 15)
+areaid_ij = polygons(81, 17)
+areaid_zr = polygons(81, 18)
+areaid_ed = polygons(81, 19)
+areaid_de = polygons(81, 23)
+areaid_rd = polygons(81, 24)
+areaid_dn = polygons(81, 50)
+areaid_cr = polygons(81, 51)
+areaid_cd = polygons(81, 52)
+areaid_st = polygons(81, 53)
+areaid_op = polygons(81, 54)
+areaid_en = polygons(81, 57)
+areaid_en20 = polygons(81, 58)
+areaid_le = polygons(81, 60)
+areaid_hl = polygons(81, 63)
+areaid_sd = polygons(81, 70)
+areaid_po = polygons(81, 81)
+areaid_it = polygons(81, 84)
+areaid_et = polygons(81, 101)
+areaid_lvt = polygons(81, 108)
+areaid_re = polygons(81, 125)
+areaid_ag = polygons(81, 79)
+poly_rs = polygons(66, 13)
+diff_rs = polygons(65, 13)
+pwell_rs = polygons(64, 13)
+li_rs = polygons(67, 13)
+cfom = polygons(22, 20)
+
+
+# Define a new custom function that selects polygons by their number of holes:
+# It will return a new layer containing those polygons with min to max holes.
+# max can be nil to omit the upper limit.
+class DRC::DRCLayer
+  def with_holes(min, max)
+    new_data = RBA::Region::new
+    self.data.each do |p|
+      if p.holes &gt;= (min || 0) &amp;&amp; (!max || p.holes &lt;= max)
+        new_data.insert(p)
+      end
+    end
+    DRC::DRCLayer::new(@engine, new_data)
+  end
+end
+
+# DRC section
+########################
+info("DRC section")
+
+if FEOL
+info("FEOL section")
+gate = diff &amp; poly
+
+#   dnwell
+dnwell.width(3.0, euclidian).output("dnwell.2", "dnwell.2 : min. dnwell width : 3.0um")
+dnwell.not(uhvi).not(areaid_po).isolated(6.3, euclidian).output("dnwell.3", "dnwell.3 : min. dnwell spacing : 6.3um")
+dnwell.and(pnp).output("dnwell.4", "dnwell.4 : dnwell must not overlap pnp")
+dnwell.and(psdm).edges.not(psdm.edges).output("dnwell.5", "p+ must not straddle dnwell")
+# dnwell.6 rue not coded
+
+#   nwell
+nwell.width(0.84, euclidian).output("nwell.1", "nwell.1 : min. nwell width : 0.84um")
+nwell.isolated(1.27, euclidian).output("nwell.2a", "nwell.2a : min. nwell spacing (merged if less) : 1.27um")
+# rule nwell.4 is suitable for digital cells
+#nwell.not(uhvi).not(areaid_en20).not_interacting(tap.and(licon).and(li)).output("nwell.4", "nwell4 : all nwell exempt inside uhvi must contain a n+tap")
+nwell.enclosing(dnwell.not(uhvi).not(areaid_po), 0.4, euclidian).output("nwell.5", "nwell.5 : min. nwell enclosing dnwell exempt unside uhvi : 0.4um")
+dnwell.enclosing(nwell.not(uhvi), 1.03, euclidian).output("nwell.6", "nwell.6 : min. dnwell enclosing nwell exempt unside uhvi : 1.03um")
+dnwell.separation(nwell, 4.5, euclidian).output("nwell.7", "nwell.7 : min. dnwell separation nwell : 4.5um")
+
+#   pwbm
+pwbm.not(uhvi).output("pwbm", "pwbm must be inside uhvi")
+dnwell.and(uhvi).edges.not(pwbm).output("pwbm.4", "pwbm.4 : dnwell inside uhvi must be enclosed by pwbm")
+
+#   pwde
+pwde.not(pwbm).output("pwdem.3", "pwdem.3 : pwde must be inside pwbm")
+pwde.not(uhvi).output("pwdem.4", "pwdem.4 : pwde must be inside uhvi")
+pwde.not(dnwell).output("pwdem.5", "pwdem.5 : pwde must be inside dnwell")
+
+#   hvtp
+#hvtp.not(nwell).output("hvtp", "hvtp must inside nwell")
+hvtp.width(0.38, euclidian).output("hvtp.1", "hvtp.1 : min. hvtp width : 0.38um")
+hvtp.isolated(0.38, euclidian).output("hvtp.2", "hvtp.2 : min. hvtp spacing : 0.38um")
+hvtp.enclosing(gate.and(psdm), 0.18, euclidian).output("hvtp.3", "hvtp.3 : min. hvtp enclosure of pfet gate : 0.18um")
+hvtp.separation(gate.and(psdm), 0.18, euclidian).output("hvtp.4", "hvtp.4 : min. hvtp spacing pfet gate: 0.18um")
+hvtp.with_area(0..0.265).output("hvtp.5", "hvtp.5 : min. hvtp area : 0.265um²")
+
+#   hvtr
+hvtr.width(0.38, euclidian).output("hvtr.1", "hvtr.1 : min. hvtr width : 0.38um")
+hvtr.isolated(0.38, euclidian).output("hvtr.2", "hvtr.2 : min. hvtr spacing : 0.38um")
+
+#   lvtn
+lvtn.width(0.38, euclidian).output("lvtn.1", "lvtn.1 : min. lvtn width : 0.38um")
+lvtn.isolated(0.38, euclidian).output("lvtn.2", "lvtn.2 : min. lvtn spacing : 0.38um")
+lvtn.separation(diff.and(poly).not(uhvi), 0.18, euclidian).output("lvtn.3a", "lvtn.3a : min. lvtn spacing to gate : 0.18um")
+lvtn.separation(diff.and(nwell).not(poly), 0.235, projection).output("lvtn.3b", "lvtn.3b : min. lvtn spacing to pfet s/d : 0.18um")
+lvtn.enclosing(gate.not(uhvi), 0.18, euclidian).output("lvtn.4b", "lvtn.4b : min. lvtn enclosing to gate : 0.18um")
+lvtn.separation(hvtp, 0.38, euclidian).output("lvtn.9", "lvtn.9 : min. lvtn spacing hvtp : 0.38um")
+nwell.not_interacting(gate.and(nwell.not(hvi).not(areaid_ce))).enclosing(lvtn.not(uhvi), 0.18, euclidian).polygons.without_area(0).output("lvtn.4b", "lvtn.4b : min. lvtn enclosure of gate : 0.18um")
+lvtn.separation(nwell.inside(areaid_ce), 0.38, euclidian).output("lvtn.12", "lvtn.12 : min. lvtn spacing nwell inside areaid.ce : 0.38um")
+lvtn.with_area(0..0.265).output("lvtn.13", "lvtn.13 : min. lvtn area : 0.265um²")
+
+#   ncm
+ncm.and(tap.and(nwell).or(diff.not(nwell))).output("ncm.x.3", "ncm.x.3 : ncm must not overlap n+diff")
+ncm.width(0.38, euclidian).output("ncm.1", "ncm.1 : min. ncm width : 0.38um")
+ncm.isolated(0.38, euclidian).output("ncm.2", "ncm.2 : min. ncm spacing manual merge if smaller : 0.38um")
+ncm.enclosing(diff.and(nwell), 0.18, euclidian).output("ncm.3", "ncm.3 : min. ncm enclosure of p+diff : 0.18um")
+ncm.separation(lvtn.and(diff), 0.23, euclidian).output("ncm.5", "ncm.5 : min. ncm spacing lvtn diff : 0.23um")
+ncm.separation(diff.not(nwell), 0.2, euclidian).output("ncm.6", "ncm.6 : min. ncm spacing nfet : 0.2um")
+ncm.with_area(0..0.265).output("ncm.7", "ncm.13 : min. ncm area : 0.265um²")
+
+#   diff-tap
+difftap = diff + tap
+difftap.width(0.15, euclidian).output("difftap.1", "difftap.1 : min. difftap width : 0.15um")
+not_in_cell1 = layout(source.cell_obj).select("s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b" , "-s8fpls_pl8", "-s8fpls_rdrv4" , "-s8fpls_rdrv4f", "-s8fpls_rdrv8")
+not_in_cell1_diff = not_in_cell1.input(65, 20)
+not_in_cell1_diff.not(areaid_sc).not(poly).edges.and(gate.edges).with_length(0,0.42).output("difftap.2", "difftap.2: min. gate (exempt areaid.sc) width : 0.42um")
+diff.and(areaid_sc).not(poly).edges.and(gate.edges).with_length(0,0.36).output("difftap.2", "difftap.2: min. gate inside areaid.sc width : 0.36um")
+difftap.isolated(0.27, euclidian).output("difftap.3", "difftap.3 : min. difftap spacing : 0.27um")
+tap.edges.and(diff.edges).with_length(0,0.29).output("difftap.4", "difftap.4 : min. tap bound by diffusion : 0.29um")
+tap.edges.and(diff.edges).space(0.4, projection).output("difftap.5", "difftap.5 : min. tap bound by 2 diffusions : 0.4um")
+(tap.edges.and(diff.edges)).extended(0.01, 0.01, 0, 0, false).not(tap.and(diff)).and(diff.or(tap)).output("difftap.6", "difftap.6 : diff and tap not allowed to extend beyong their abutting ege")
+tap.edges.not_interacting(diff.edges).separation(diff.edges, 0.13, euclidian).output("difftap.7", "difftap.7 : min. diff/tap spacing to non-coincident diff edge : 0.13um")
+diff.edges.not_interacting(tap.edges).separation(tap.edges, 0.13, euclidian).output("difftap.7", "difftap.7 : min. diff/tap spacing to non-coincident tap edge : 0.13um")
+nwell.enclosing(diff.not(uhvi).and(psdm), 0.18, euclidian).output("difftap.8", "difftap.8 : min. p+diff enclosure by nwell : 0.18um")
+diff.not(uhvi).and(nsdm).separation(nwell, 0.34, euclidian).output("difftap.9", "difftap.9 : min. n+diff spacing to nwell : 0.34um")
+nwell.enclosing(tap.not(uhvi).and(nsdm), 0.18, euclidian).output("difftap.10", "difftap.10 : min. n+tap enclosure by nwell : 0.18um")
+tap.not(uhvi).and(psdm).separation(nwell, 0.13, euclidian).output("difftap.11", "difftap.11 : min. p+tap spacing to nwell : 0.13um")
+
+#   tunm
+tunm.width(0.41, euclidian).output("tunm.1", "tunm.1 : min. tunm width : 0.41um")
+tunm.isolated(0.5, euclidian).output("tunm.2", "tunm.2 : min. tunm spacing : 0.5um")
+tunm.enclosing(gate, 0.095, euclidian).output("tunm.3", "tunm.3 : min. tunm beyond gate : 0.095um")
+tunm.separation(gate.not_interacting(tunm), 0.095, euclidian).output("tunm.4", "tunm.4 : min. tunm spacing to gate outside tunm: 0.095um")
+gate.and(tunm).edges.not(gate.edges).output("tunm.5", "tunm.5 : gate must not straddle tunm")
+tunm.not(dnwell).output("tunm.6a", "tunm.6a : tunm not allowed outside dnwell")
+tunm.with_area(0..0.672).output("tunm.7", "tunm.7 : min. tunm area : 0.672um²")
+
+#   poly
+poly.width(0.15, euclidian).output("poly.1a", "poly.1a : min. poly width : 0.15um")
+poly.not(diff).edges.and(gate.and(lvtn).edges).space(0.35, euclidian).output("poly.1b", "poly.1b: min. lvtn gate width : 0.35um")
+poly.isolated(0.21, euclidian).output("poly.2", "poly.2 : min. poly spacing : 0.21um")
+poly.and(rpm.or(urpm).or(poly_rs)).width(0.33, euclidian).output("poly.3", "poly.3 : min. poly resistor width : 0.33um")
+poly.not(gate).separation(diff, 0.075, projection).polygons.without_area(0).output("poly.4", "poly.4 : min. poly on field spacing to diff : 0.075um")
+poly.not(gate).separation(tap, 0.055, euclidian).output("poly.5", "poly.5 : min. poly on field spacing to tap : 0.055um")
+gate.separation(tap, 0.3, projection).polygons.and(diff).output("poly.6", "poly.6 : min. gate spacing to tap : 0.3um")
+diff.enclosing(gate, 0.25, projection).polygons.without_area(0).output("poly.7", "poly.7 : min. source/drain length : 0.25um")
+poly.enclosing(gate, 0.13, projection).polygons.without_area(0).output("poly.8", "poly.8 : min. poly extention gate (endcap) : 0.13um")
+poly.and(rpm.or(urpm).or(poly_rs)).separation(poly.or(difftap), 0.48, euclidian).polygons.without_area(0).output("poly.9", "poly.9 : min. poly resistor space to poly or diff/tap : 0.48um")
+diff.merged.edges.end_segments(0.01).and(poly).output("poly.10", "poly.10 : poly must not overlap diff corner")
+gate.with_angle(0 .. 90).output("poly.11", "poly.11 : non 90 degree angle gate")
+not_in_cell3 = layout(source.cell_obj).select("s8fgvr_n_fg2")
+not_in_cell3_poly = not_in_cell3.input(66, 20)
+not_in_cell3_poly.not(hvi).not(nwell.not(hvi)).and(tap).output("poly.12", "poly.12 : poly must not overlap tap")
+poly.and(diff_rs).output("poly.15", "poly.15 : poly must not overlap diff resistor")
+
+#   rpm
+rpm.width(1.27, euclidian).output("rpm.1a", "rpm.1a : min. rpm width : 1.27um")
+rpm.isolated(0.84, euclidian).output("rpm.2", "rpm.2 : min. rpm spacing : 0.84um")
+rpm.enclosing(poly.and(poly_rs).and(psdm), 0.2, euclidian).output("rpm.3", "rpm.3 : min. rpm enclosure of poly resistor : 0.2um")
+psdm.enclosing(poly.and(poly_rs).and(rpm), 0.11, euclidian).output("rpm.4", "rpm.4 : min. psdm enclosure of poly resistor : 0.11um")
+npc.enclosing(poly.and(poly_rs).and(rpm), 0.095, euclidian).output("rpm.5", "rpm.5 : min. npc enclosure of poly resistor : 0.095um")
+rpm.separation(nsdm, 0.2, euclidian).output("rpm.6", "rpm.6 : min. rpm spacing nsdm: 0.2um")
+rpm.separation(poly, 0.2, euclidian).output("rpm.7", "rpm.7 : min. rpm spacing poly: 0.2um")
+rpm.and(poly).edges.not(poly.edges).output("rpm.8", "rpm.8 : poly must not straddle rpm")
+poly.and(poly_rs).and(rpm).separation(hvntm, 0.185, euclidian).output("rpm.9", "rpm.9 : min. poly resistor spacing hvntm: 0.185um")
+rpm.and(pwbm).output("rpm.10", "rpm.107 : min. rpm spacing pwbm: na")
+
+#   varac
+varac = poly &amp; tap &amp; (nwell - hvi) - areaid_ce
+tap.not(poly).edges.and(varac.edges).space(0.18, euclidian).output("varac.1", "varac.1: min. varac channel length : 0.18um")
+tap.and(poly).edges.and(varac.edges).space(1.0, euclidian).output("varac.2", "varac.2: min. varac channel wdth : 1.0um")
+varac.separation(hvtp, 0.18, euclidian).output("varac.3", "varac.3: min. varac channel space to hvtp : 0.18um")
+varac.separation(licon.and(tap), 0.25, euclidian).output("varac.4", "varac.4: min. varac channel space to licon on tap : 0.25um")
+nwell.enclosing(poly.overlapping(varac), 0.15, euclidian).output("varac.5", "varac.5: min. nwell enclosure of poly overlapping varac channel : 0.15um")
+tap.overlapping(varac).separation(difftap, 0.27, euclidian).polygons.without_area(0).output("varac.6", "varac.6: min. varac channel tap space to difftap : 0.27um")
+nwell.overlapping(varac).and(diff.and(nwell)).output("varac.7", "varac.7:  nwell overlapping varac channel must not overlap p+diff")
+
+#   photo
+photodiode = dnwell &amp; areaid_po
+photodiode.edges.without_length(3.0).output("photo.2", "photo.2 : minimum/maximum width of photodiode : 3.0um")
+photodiode.isolated(5.0, euclidian).output("photo.3", "photo.3 : mini. photodiode spacing : 5.0um")
+photodiode.separation(dnwell, 5.3, euclidian).output("photo.4", "photo.4 : mini. photodiode spacing to dnwell : 5.3um")
+areaid_po.not(dnwell).output("photo.5.6", "photo.5.6 : photodiode edges must coincide areaid.po and enclosed by dnwell")
+photodiode.not(tap.not(nwell).holes).output("photo.7", "photo.7 : photodiode must be enclosed by p+tap ring")
+photodiode.and(nwell).edges.without_length(0.84).output("photo.8", "photo.8 : minimum/maximum width of nwell inside photodiode : 0.84um")
+areaid_po.edges.and(photodiode.and(nwell).sized(1.08)).without_length(12.0).output("photo.9", "photo.9 : minimum/maximum enclosure of nwell by photodiode : 1.08um")
+photodiode.and(tap).edges.without_length(0.41).output("photo.10", "photo.10 : minimum/maximum width of tap inside photodiode : 0.41um")
+
+#   npc
+npc.width(0.27, euclidian).output("npc.1", "npc.1 : min. npc width : 0.27um")
+npc.isolated(0.27, euclidian).output("npc.2", "npc.2 : min. npc spacing, should be mnually merge if less : 0.27um")
+npc.separation(gate, 0.09, euclidian).output("npc.4", "npc.4 : min. npc spacing to gate : 0.09um")
+
+#   nsdm/psdm
+npsdm = nsdm + psdm
+nsdm.width(0.38, euclidian).output("nsdm.1", "nsdm.1 : min. nsdm width : 0.38um")
+psdm.width(0.38, euclidian).output("psdm.1", "psdm.1 : min. psdm width : 0.38um")
+nsdm.isolated(0.38, euclidian).output("n/psdm.1", "n/psdm.1 : min. nsdm spacing, should be mnually merge if less : 0.38um")
+psdm.isolated(0.38, euclidian).output("n/psdm.1", "n/psdm.1 : min. psdm spacing, should be mnually merge if less : 0.38um")
+npsdm.enclosing(diff, 0.125, euclidian).polygons.not(tap.sized(0.125)).output("n/psdm.5a", "n/psdm.5a : min. n/psdm enclosure diff except butting edge : 0.125um")
+npsdm.enclosing(tap, 0.125, euclidian).polygons.not(diff.sized(0.125)).output("n/psdm.5b", "n/psdm.5b : min. n/psdm enclosure tap except butting edge : 0.125um")
+tap.edges.and(diff.edges).not(npsdm).output("n/psdm.6", "n/psdm.6 : min. n/psdm enclosure of butting edge : 0.0um")
+nsdm.and(difftap).separation(psdm.and(difftap), 0.13, euclidian).polygons.without_area(0).output("n/psdm.7", "n/psdm.7 : min. nsdm diff spacing to psdm diff except butting edge : 0.13um")
+diff.and((nsdm.and(nwell)).or(psdm.not(nwell))).output("n/psdm.8", "n/psdm.8 : diff should be the opposite type of well/substrate underneath")
+tap.and((nsdm.not(nwell)).or(psdm.and(nwell))).output("n/psdm.8", "n/psdm.8 : tap should be the same type of well/substrate underneath")
+tap.and(diff).without_area(0).output("tap and diff", "tap and diff must not overlap")
+nsdm.with_area(0..0.265).output("n/psdm.10a", "n/psdm.10a : min. nsdm area : 0.265um²")
+psdm.with_area(0..0.265).output("n/psdm.10b", "n/psdm.10b : min. psdm area : 0.265um²")
+
+#   licon
+licon.not(poly.interacting(poly_rs).and(rpm)).edges.without_length(0.17).output("licon.1", "licon.1 : minimum/maximum width of licon : 0.17um")
+licon.and(poly.interacting(poly_rs).and(rpm)).not_interacting((licon.and(poly.interacting(poly_rs).and(rpm)).edges.with_length(0.19)).or(licon.and(poly.interacting(poly_rs).and(rpm)).edges.with_length(2.0))).output("licon.1b/c", "licon.1b/c : minimum/maximum width/length of licon inside poly resistor : 2.0/0.19um")
+licon.isolated(0.17, euclidian).output("licon.2", "licon.2 : min. licon spacing : 0.17um")
+licon.and(poly.interacting(poly_rs).and(rpm)).edges.with_length(0.19).space(0.35, euclidian).output("licon.2b", "licon.2b : min. licon 0.19um edge on resistor spacing : 0.35um")
+licon.interacting(licon.and(poly.interacting(poly_rs).and(rpm)).edges.with_length(2.0)).separation(licon.and(poly.interacting(poly_rs).and(rpm)), 0.51, euclidian).output("licon.2c", "licon.2c : min. licon 2.0um edge on resistor spacing : 0.51um")
+licon.and(poly.interacting(poly_rs).and(rpm)).separation(licon.not(poly.interacting(poly_rs).and(rpm)), 0.51, euclidian).output("licon.2d", "licon.2d : min. licon on resistor spacing other licon : 0.51um")
+# rule licon.3 not coded
+licon.not(li).not(poly.or(diff).or(tap)).output("licon.4", "licon.4 : min. licon must overlap li and (poly or tap or diff) ")
+diff.enclosing(licon, 0.04, euclidian).output("licon.5", "licon.5 : min. diff enclosure of licon : 0.04um")
+tap.edges.and(diff.edges).separation(licon.and(tap).edges, 0.06, euclidian).output("licon.6", "licon.6 : min. abutting edge spacing to licon tap : 0.06um")
+licon_edges_with_less_enclosure_tap = tap.enclosing(licon, 0.12, projection).second_edges
+opposite1 = (licon.edges - licon_edges_with_less_enclosure_tap).width(0.17 + 1.dbu, projection).polygons
+licon.not_interacting(opposite1).output("licon.7", "licon.7 : min. tap enclosure of licon by one of 2 opposite edges : 0.12um")
+poly.enclosing(licon, 0.05, euclidian).output("licon.8", "licon.8 : min. poly enclosure of licon : 0.05um")
+licon008 = licon.interacting(poly.enclosing(licon, 0.08, euclidian).polygons)
+licon_edges_with_less_enclosure_poly = poly.enclosing(licon, 0.08, projection).second_edges
+opposite2 = (licon.edges - licon_edges_with_less_enclosure_poly).width(0.17 + 1.dbu, projection).polygons
+licon008.not_interacting(opposite2).output("licon.8a", "licon.8a : min. poly enclosure of licon by one of 2 opposite edges : 0.08um")
+# rule licon.9 not coded
+licon.and(tap.and(nwell.not(hvi))).separation(varac, 0.25, euclidian).output("licon.10", "licon.10 : min. licon spacing to varac channel : 0.25um")
+not_in_cell4 = layout(source.cell_obj).select("-s8fs_gwdlvx4", "-s8fs_gwdlvx8", "-s8fs_hvrsw_x4", "-s8fs_hvrsw8", "-s8fs_hvrsw264", "-s8fs_hvrsw520", "-s8fs_rdecdrv", "-s8fs_rdec8”, “s8fs_rdec32", "-s8fs_rdec264", "-s8fs_rdec520")
+not_in_cell4_licon = not_in_cell4.input(66, 44)
+not_in_cell4_licon.and(diff.or(tap)).separation(gate.not(areaid_sc), 0.055, euclidian).output("licon.11", "licon.11 : min. licon spacing to gate : 0.055um")
+licon.and(diff.or(tap)).separation(gate.and(areaid_sc), 0.05, euclidian).output("licon.11a", "licon.11a : min. licon spacing to gate inside areaid.sc : 0.05um")
+in_cell4 = layout(source.cell_obj).select("+s8fs_gwdlvx4", "+s8fs_gwdlvx8", "+s8fs_hvrsw_x4", "+s8fs_hvrsw8", "+s8fs_hvrsw264", "+s8fs_hvrsw520")
+in_cell4_licon = in_cell4.input(66, 44)
+in_cell4_licon.and(diff.or(tap)).separation(gate, 0.04, euclidian).output("licon.11c", "licon.11c : min. licon spacing to gate for specific cells: 0.04um")
+# rules 11.b , 11.d not coded
+diff.interacting(gate).not(diff.interacting(gate).width(5.7, euclidian).polygons).output("licon.12", "licon.12 : max. sd width without licon : 5.7um")
+licon.and(diff.or(tap)).separation(npc, 0.09, euclidian).output("licon.13", "licon.13 : min. difftap licon spacing to npc : 0.09um")
+licon.and(poly).separation(diff.or(tap), 0.19, euclidian).output("licon.14", "licon.14 : min. poly licon spacing to difftap : 0.19um")
+npc.enclosing(licon.and(poly), 0.1, euclidian).output("licon.15", "licon.15 : min. npc enclosure of poly-licon : 0.1um")
+# rule licon.16 not applicable for the diff for the nmos of a nand gates or the pmos of a nor gates
+#diff.not(gate).not_interacting(licon).output("licon.16", "licon.16 : diff must enclose one licon")
+tap.not(uhvi).not_interacting(licon).output("licon.16", "licon.16 : tap must enclose one licon")
+poly.and(tap).edges.not(tap.edges).output("licon.17", "licon.17 : tap must not straddle poly")
+npc.not_interacting(licon.and(poly)).output("licon.18", "licon.18 : npc mut enclosed one poly-licon")
+
+#   vpp
+vpp.width(1.43, euclidian).output("vpp.1", "vpp.1 : min. vpp width : 1.43um")
+# rules 1.b, 1.c not coded
+vpp.and(poly.or(difftap)).output("vpp.3", "vpp.3 : vpp must not overlapp poly or diff or tap")
+vpp.and(nwell).edges.not(vpp.edges).output("vpp.4", "vpp.4 : vpp must not straddle nwell")
+vpp.and(dnwell).edges.not(vpp.edges).output("vpp.4", "vpp.4 : vpp must not straddle dnwell")
+vpp.and(poly.or(li).or(m1).or(m2)).separation(poly.or(li).or(m1).or(m2), 1.5, euclidian).polygons.with_area(2.25,nil).output("vpp.5", "vpp.5 : min. vpp spacing to poly or li or m1 or m2 : 1.5um")
+vpp.with_area(0..area(vpp.and(m3))*0.25).output("vpp.5a", "vpp.5a : max. m3 density in vpp : 0.25")
+vpp.with_area(0..area(vpp.and(m4))*0.3).output("vpp.5b", "vpp.5b : max. m4 density in vpp : 0.3")
+vpp.with_area(0..area(vpp.and(m5))*0.4).output("vpp.5c", "vpp.5c : max. m5 density in vpp : 0.4")
+nwell.enclosing(vpp, 1.5, euclidian).output("vpp.8", "vpp.8 : nwell enclosure of vpp : 1.5")
+vpp.separation(nwell, 1.5, euclidian).polygons.without_area(0).output("vpp.9", "vpp.9 : vpp spacing to nwell : 1.5")
+# rule vpp.10 not coded
+# rule vpp.11 not coded because moscap is not defined properly by any gds layer
+# rules vpp.12a, 12b, 12c not coded because specific to one cell
+if backend_flow = CU
+  m1.separation(vpp.and(m1), 0.16, euclidian).polygons.without_area(0).output("vpp.13", "vpp.13 : m1 spacing to m1inside vpp : 0.16")
+end
+
+# CAPM
+capm.width(1.0, euclidian).output("capm.1", "capm.1 : min. capm width : 1.0um")
+capm.isolated(0.84, euclidian).output("capm.2a", "capm.2a : min. capm spacing : 0.84um")
+m2.interacting(capm).isolated(1.2, euclidian).output("capm.2b", "capm.2b : min. capm spacing : 1.2um")
+m2.enclosing(capm, 0.14, euclidian).output("capm.3", "capm.3 : min. m2 enclosure of capm : 0.14um")
+capm.enclosing(via2, 0.14, euclidian).output("capm.4", "capm.4 : min. capm enclosure of via2 : 0.14um")
+capm.separation(via2, 0.14, euclidian).output("capm.5", "capm.5 : min. capm spacing to via2 : 0.14um")
+capm.sized(-20.0).sized(20.0).output("capm.6", "capm.6 : max. capm lenght/width : 20um")
+capm.with_angle(0 .. 90).output("capm.7", "capm.7 : capm not rectangle")
+capm.separation(via, 0.14, euclidian).polygons.without_area(0).output("capm.8", "capm.8 : min. capm spacing to via : 0.14um")
+capm.and(nwell).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle nwell")
+capm.and(diff).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle diff")
+capm.and(tap).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle tap")
+capm.and(poly).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle poly")
+capm.and(li).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle li")
+capm.and(m1).edges.not(capm.edges).output("capm.10", "capm.10 : capm must not straddle m1")
+capm.separation(m2.not_interacting(capm),  0.14, euclidian).output("capm.11", "capm.11 : min. capm spacing to m2 not overlapping capm : 0.5um")
+
+end #FEOL
+
+if BEOL
+info("BEOL section")
+
+#   li
+not_in_cell5 = source.select("-s8rf2_xcmvpp_hd5_*")
+not_in_cell5_li = not_in_cell5.polygons(li_wildcard)
+not_in_cell5_li.width(0.17, euclidian).output("li.1", "li.1 : min. li width : 0.17um")
+
+in_cell5_li = li - not_in_cell5_li
+in_cell5_li.width(0.14, euclidian).output("li.1a", "li.1a : min. li width for the cells s8rf2_xcmvpp_hd5_* : 0.14um")
+
+# rule li.2 not coded
+
+not_in_cell5_li.space(0.17, euclidian).output("li.3", "li.3 : min. li spacing : 0.17um")
+in_cell5_li.space(0.14, euclidian).output("li.3a", "li.3a : min. li spacing for the cells s8rf2_xcmvpp_hd5_* : 0.14um")
+licon08 = licon.interacting(li.enclosing(licon, 0.08, euclidian).polygons)
+licon_edges_with_less_enclosure_li = li.enclosing(licon, 0.08, projection).second_edges
+opposite3 = (licon.edges - licon_edges_with_less_enclosure_li).width(0.17 + 1.dbu, projection).polygons
+licon08.not_interacting(opposite3).output("li.5", "li.5 : min. li enclosure of licon of 2 opposite edges : 0.08um")
+li.with_area(0..0.0561).output("li.6", "li.6 : min. li area : 0.0561um²")
+
+#   ct
+mcon.edges.without_length(0.17).output("ct.1", "ct.1 : minimum/maximum width of mcon : 0.17um")
+mcon.space(0.19, euclidian).output("ct.2", "ct.2 : min. mcon spacing : 0.19um")
+# rule ct.3 not coded
+mcon.not(li).output("ct.4", "ct.4 : mcon should covered by li")
+if backend_flow = CU
+  li.interacting(li.and(m1).not(mcon).with_holes(1,10)).enclosing(mcon, 0.2, euclidian).output("ct.irdrop.1", "ct.irdrop.1 : min. li enclsoure of 1..10 mcon : 0.2um")
+  li.interacting(li.and(m1).not(mcon).with_holes(11,100)).enclosing(mcon, 0.3, euclidian).output("ct.irdrop.2", "ct.irdrop.2 : min. li enclsoure of 11..100 mcon : 0.3um")
+end
+
+#   m1
+m1.width(0.14, euclidian).output("m1.1", "m1.1 : min. m1 width : 0.14um")
+
+huge_m1 = m1.sized(-1.5).sized(1.5)
+non_huge_m1 = m1 - huge_m1
+
+non_huge_m1.space(0.14, euclidian).output("m1.2", "m1.2 : min. m1 spacing : 0.14um")
+
+(huge_m1.separation(non_huge_m1, 0.28, euclidian) + huge_m1.space(0.28, euclidian)).output("m1.3ab", "m1.3ab : min. 3um.m1 spacing m1 : 0.28um")
+
+not_in_cell6 = layout(source.cell_obj).select("-s8cell_ee_plus_sseln_a", "-s8cell_ee_plus_sseln_b", "-s8cell_ee_plus_sselp_a", "-s8cell_ee_plus_sselp_b", "-s8fpls_pl8", "-s8fs_cmux4_fm")
+not_in_cell6_m1 = not_in_cell6.input(m1_wildcard)
+not_in_cell6_m1.enclosing(mcon, 0.03, euclidian).output("m1.4", "m1.4 : min. m1 enclosure of mcon : 0.03um")
+in_cell6 = layout(source.cell_obj).select("+s8cell_ee_plus_sseln_a", "+s8cell_ee_plus_sseln_b", "+s8cell_ee_plus_sselp_a", "+s8cell_ee_plus_sselp_b", "+s8fpls_pl8", "+s8fs_cmux4_fm")
+in_cell6_m1 = in_cell6.input(m1_wildcard)
+in_cell6_m1.enclosing(mcon, 0.005, euclidian).output("m1.4a", "m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um")
+m1.with_area(0..0.083).output("m1.6", "m1.6 : min. m1 area : 0.083um²")
+m1.holes.with_area(0..0.14).output("m1.7", "m1.7 : min. m1 holes area : 0.14um²")
+if backend_flow = AL
+  mcon06 = mcon.interacting(poly.enclosing(m1, 0.06, euclidian).polygons)
+  mcon_edges_with_less_enclosure_m1 = m1.enclosing(mcon, 0.06, projection).second_edges
+  opposite4 = (mcon.edges - mcon_edges_with_less_enclosure_m1).width(0.17 + 1.dbu, projection).polygons
+  mcon06.not_interacting(opposite4).output("m1.5", "m1.5 : min. m1 enclosure of mcon of 2 opposite edges : 0.06um")
+  # rule m1.pd.1, rule m1.pd.2a, rule m1.pd.2b not coded
+end
+if bakend_flow = CU
+  m1.sized(-2.0).sized(2.0).output("m1.11", "m1.11 : max. m1 width after slotting : 4.0um")
+  # rule m1.12 not coded because inconsistent with m1.11
+  # rule m1.13, m1.14, m1.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759
+end
+
+#   via
+#rule via.3 not coded
+via.not(m1).output("via.4c.5c", "via.4c.5c : m1 must enclose all via")
+if backend_flow = AL
+  via.not(areaid_mt).edges.without_length(0.15).output("via.1a", "via.1a : minimum/maximum width of via : 0.15um")
+  via.and(areaid_mt).not_interacting((via.and(areaid_mt).edges.without_length(0.15)).or(via.and(areaid_mt).edges.without_length(0.23)).or(via.and(areaid_mt).edges.without_length(0.28))).output("via.1b", "via.1b : minimum/maximum width of via in areaid.mt: 0.15um or 0.23um or 0.28um")
+  via.isolated(0.17, euclidian).output("via.2", "via.2 : min. via spacing : 0.17um")
+  m1.enclosing(via.not_interacting(via.edges.without_length(0.15)), 0.055, euclidian).output("via.4a", "via.4a : min. m1 enclosure of 0.15um via : 0.055um")
+  m1.enclosing(via.not_interacting(via.edges.without_length(0.23)), 0.03, euclidian).output("via.4b", "via.4b : min. m1 enclosure of 0.23um via : 0.03um")
+  via1_edges_with_less_enclosure_m1 = m1.enclosing(via.not_interacting(via.edges.without_length(0.15)), 0.085, projection).second_edges
+  opposite5 = (via.not_interacting(via.edges.without_length(0.15)).edges - via1_edges_with_less_enclosure_m1).width(0.15 + 1.dbu, projection).polygons
+  via.not_interacting(via.edges.without_length(0.15)).not_interacting(opposite5).output("via1.5a", "via1.5a : min. m1 enclosure of 0.15um via of 2 opposite edges : 0.085um")
+  via2_edges_with_less_enclosure_m1 = m1.enclosing(via.not_interacting(via.edges.without_length(0.23)), 0.06, projection).second_edges
+  opposite6 = (via.not_interacting(via.edges.without_length(0.23)).edges - via2_edges_with_less_enclosure_m1).width(0.23 + 1.dbu, projection).polygons
+  via.not_interacting(via.edges.without_length(0.23)).not_interacting(opposite6).output("via1.5b", "via1.5b : min. m1 enclosure of 0.23um via of 2 opposite edges : 0.06um")
+end
+if backend_flow = CU
+  via.not(areaid_mt).edges.without_length(0.18).output("via.11", "via.11 : minimum/maximum width of via : 0.18um")
+  via.isolated(0.13, euclidian).output("via.12", "via.12 : min. via spacing : 0.13um")
+  # rule via.13 not coded because not understandable
+  via1_edges_with_less_enclosure_m1 = m1.enclosing(via, 0.04, projection).second_edges
+  opposite5 = (via.edges - via1_edges_with_less_enclosure_m1).width(0.18 + 1.dbu, projection).polygons
+  via.not_interacting(opposite5).output("via1.14", "via1.14 : min. m1 enclosure of 0.04um via of 2 opposite edges : 0.04um")
+  # rules via.irdrop.1, via.irdrop.2, via.irdrop.3, via.irdrop.4 not coded because not understandable
+end
+
+#   m2
+m2.width(0.14, euclidian).output("m2.1", "m2.1 : min. m2 width : 0.14um")
+
+huge_m2 = m2.sized(-1.5).sized(1.5)
+non_huge_m2 = m2 - huge_m2
+
+non_huge_m2.space(0.14, euclidian).output("m2.2", "m2.2 : min. m2 spacing : 0.14um")
+
+(huge_m2.separation(non_huge_m2, 0.28, euclidian) + huge_m2.space(0.28, euclidian)).output("m2.3ab", "m2.3ab : min. 3um.m2 spacing m2 : 0.28um")
+
+# rule m2.3c not coded
+m2.with_area(0..0.0676).output("m2.6", "m2.6 : min. m2 area : 0.0676um²")
+m2.holes.with_area(0..0.14).output("m2.7", "m2.7 : min. m2 holes area : 0.14um²")
+via.not(m2).output("m2.via", "m2.via : m2 must enclose via")
+if backend_flow = AL
+  m2.enclosing(via, 0.055, euclidian).output("m2.4", "m2.4 : min. m2 enclosure of via : 0.055um")
+  via_edges_with_less_enclosure_m2 = m2.enclosing(via, 0.085, projection).second_edges
+  opposite7 = (via.edges - via_edges_with_less_enclosure_m2).width(0.2 + 1.dbu, projection).polygons
+  via.not_interacting(opposite7).output("m2.5", "m2.5 : min. m2 enclosure of via of 2 opposite edges : 0.085um")
+  # rule m2.pd.1, rule m2.pd.2a, rule m2.pd.2b not coded
+end
+if bakend_flow = CU
+  m2.sized(-2.0).sized(2.0).output("m2.11", "m2.11 : max. m2 width after slotting : 4.0um")
+  # rule m2.12 not coded because inconsistent with m2.11
+  # rule m2.13, m2.14, m2.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759
+end
+
+#   via2
+#rule via233 not coded
+via2.not(m2).output("via2", "via2 : m2 must enclose all via2")
+if backend_flow = AL
+  via2.not(areaid_mt).edges.without_length(0.2).output("via2.1a", "via2.1a : minimum/maximum width of via2 : 0.2um")
+  via2.and(areaid_mt).not_interacting((via2.and(areaid_mt).edges.without_length(0.2)).or(via2.and(areaid_mt).edges.without_length(1.2)).or(via2.and(areaid_mt).edges.without_length(1.5))).output("via2.1b", "via2.1b : minimum/maximum width of via2 in areaid.mt: 0.2um or 1.2um or 1.5um")
+  via2.isolated(0.2, euclidian).output("via2.2", "via2.2 : min. via2 spacing : 0.2um")
+  m2.enclosing(via2, 0.04, euclidian).output("via2.4", "via2.4 : min. m2 enclosure of via2 : 0.04um")
+  m2.enclosing(via2.not_interacting(via2.edges.without_length(1.5)), 0.14, euclidian).output("via2.4a", "via2.4a : min. m2 enclosure of 1.5um via2 : 0.14um")
+  via2_edges_with_less_enclosure_m2 = m2.enclosing(via2, 0.085, projection).second_edges
+  opposite8 = (via2.edges - via2_edges_with_less_enclosure_m2).width(0.2 + 1.dbu, projection).polygons
+  via2.not_interacting(opposite8).output("via2.5", "via2.5 : min. m2 enclosure of via2 of 2 opposite edges : 0.085um")
+end
+if backend_flow = CU
+  via2.edges.without_length(0.21).output("via2.11", "via2.11 : minimum/maximum width of via2 : 0.21um")
+  via2.isolated(0.18, euclidian).output("via2.12", "via2.12 : min. via2 spacing : 0.18um")
+  # rule via2.13 not coded because not understandable, or not clear
+  m2.enclosing(via2, 0.035, euclidian).output("via2.14", "via2.14 : min. m2 enclosure of via2 : 0.035um")
+  # rules via2.irdrop.1, via2.irdrop.2, via2.irdrop.3, via2.irdrop.4 not coded because not understandable
+end
+
+#   m3
+m3.width(0.3, euclidian).output("m3.1", "m3.1 : min. m3 width : 0.3um")
+
+huge_m3 = m3.sized(-1.5).sized(1.5)
+non_huge_m3 = m3 - huge_m3
+
+non_huge_m3.space(0.3, euclidian).output("m3.2", "m3.2 : min. m3 spacing : 0.3um")
+
+(huge_m3.separation(non_huge_m3, 0.4, euclidian) + huge_m3.space(0.4, euclidian)).output("m3.3ab", "m3.3ab : min. 3um.m3 spacing m3 : 0.4um")
+
+# rule m3.3c not coded
+m3.with_area(0..0.24).output("m3.6", "m3.6 : min. m3 area : 0.24um²")
+via2.not(m3).output("m3.via2", "m3.via2 : m3 must enclose via2")
+if backend_flow = AL
+  m3.enclosing(via2, 0.065, euclidian).output("m3.4", "m3.4 : min. m3 enclosure of via2 : 0.065um")
+  via2_edges_with_less_enclosure_m3 = m3.enclosing(via2, 0.085, projection).second_edges
+  # m3.5 N/A
+  # opposite9 = (via2.edges - via2_edges_with_less_enclosure_m3).width(0.3 + 1.dbu, projection).polygons
+  # via2.not_interacting(opposite9).output("m3.5", "m3.5 : min. m3 enclosure of via2 of 2 opposite edges : 0.085um")
+  # rule m3.pd.1, rule m3.pd.2a, rule m3.pd.2b not coded
+end
+if bakend_flow = CU
+  m3.holes.with_area(0..0.2).output("m3.7", "m3.7 : min. m3 holes area : 0.2um²")
+  m3.sized(-2.0).sized(2.0).output("m3.11", "m3.11 : max. m3 width after slotting : 4.0um")
+  # rule m3.12 not coded because inconsistent with m3.11
+  # rule m3.13, m3.14, m3.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759
+end
+
+#   via3
+#rule via3.3 not coded
+via3.not(m3).output("via3", "via3 : m3 must enclose all via3")
+if backend_flow = AL
+  via3.not(areaid_mt).edges.without_length(0.2).output("via3.1a", "via3.1a : minimum/maximum width of via3 : 0.2um")
+  via3.and(areaid_mt).not_interacting((via3.and(areaid_mt).edges.without_length(0.2)).or(via3.and(areaid_mt).edges.without_length(0.8))).output("via3.1a", "via3.1a : minimum/maximum width of via3 in areaid.mt: 0.2um or 0.8um")
+  via3.isolated(0.2, euclidian).output("via3.2", "via3.2 : min. via3 spacing : 0.2um")
+  m3.enclosing(via3, 0.06, euclidian).output("via3.4", "via3.4 : min. m3 enclosure of via3 : 0.06um")
+  via3_edges_with_less_enclosure_m3 = m3.enclosing(via3, 0.09, projection).second_edges
+  opposite10 = (via3.edges - via3_edges_with_less_enclosure_m3).width(0.2 + 1.dbu, projection).polygons
+  via3.not_interacting(opposite10).output("via3.5", "via3.5 : min. m2 enclosure of via3 of 2 opposite edges : 0.09um")
+end
+if backend_flow = CU
+  via3.edges.without_length(0.21).output("via3.11", "via3.11 : minimum/maximum width of via3 : 0.21um")
+  via3.isolated(0.18, euclidian).output("via3.12", "via3.12 : min. via3 spacing : 0.18um")
+  m3.enclosing(via3, 0.055, euclidian).output("via3.13", "via3.13 : min. m3 enclosure of via3 : 0.055um")
+  # rule via3.14 not coded because not understandable, or not clear
+  # rules via3.irdrop.1, via3.irdrop.2, via3.irdrop.3, via3.irdrop.4 not coded because not understandable
+end
+
+#   m4
+m4.width(0.3, euclidian).output("m4.1", "m4.1 : min. m4 width : 0.3um")
+
+huge_m4 = m4.sized(-1.5).sized(1.5)
+non_huge_m4 = m4 - huge_m4
+
+non_huge_m4.space(0.3, euclidian).output("m4.2", "m4.2 : min. m4 spacing : 0.3um")
+
+(huge_m4.separation(non_huge_m4, 0.4, euclidian) + huge_m4.space(0.4, euclidian)).output("m4.5ab", "m4.5ab : min. 3um.m4 spacing m4 : 0.4um")
+
+m4.with_area(0..0.24).output("m4.4", "m4.4 : min. m4 area : 0.24um²")
+via3.not(m4).output("m4.via3", "m4.via3 : m4 must enclose via3")
+if backend_flow = AL
+  m4.enclosing(via3, 0.065, euclidian).output("m4.3", "m4.3 : min. m4 enclosure of via3 : 0.065um")
+  # m4.5 doesn't exist
+  # via3_edges_with_less_enclosure_m4 = m4.enclosing(via2, 0.085, projection).second_edges
+  # opposite9 = (via3.edges - via3_edges_with_less_enclosure_m4).width(0.3 + 1.dbu, projection).polygons
+  # via3.not_interacting(opposite9).output("m4.5", "m4.5 : min. m4 enclosure of via3 of 2 opposite edges : 0.085um")
+  # rule m4.pd.1, rule m4.pd.2a, rule m4.pd.2b not coded
+end
+if bakend_flow = CU
+  m4.holes.with_area(0..0.2).output("m4.7", "m4.7 : min. m4 holes area : 0.2um²")
+  m4.sized(-5.0).sized(5.0).output("m4.11", "m4.11 : max. m4 width after slotting : 10.0um")
+  # rule m4.12 not coded because inconsistent with m4.11
+  # rule m4.13, m4.14, m4.14a not coded : see : https://www.klayout.de/forum/discussion/comment/6759
+  m4.enclosing(via3, 0.06, euclidian).output("m4.15", "m4.15 : min. m4 enclosure of via3 : 0.06um")
+end
+
+#   via4
+via4.edges.without_length(0.8).output("via4.1a", "via4.1a : minimum/maximum width of via4 : 0.8um")
+via4.isolated(0.8, euclidian).output("via4.2", "via4.2 : min. via4 spacing : 0.8um")
+#rule via4.3 not coded
+m4.enclosing(via4, 0.19, euclidian).output("via4.4", "via4.4 : min. m4 enclosure of via4 : 0.19um")
+via4.not(m4).output("via4", "via4 : m4 must enclose all via4")
+if backend_flow = CU
+  # rules via4.irdrop.1, via4.irdrop.2, via4.irdrop.3, via4.irdrop.4 not coded because not understandable
+end
+
+#   m5
+m5.width(1.6, euclidian).output("m5.1", "m5.1 : min. m5 width : 1.6um")
+
+m5.space(1.6, euclidian).output("m5.2", "m5.2 : min. m5 spacing : 1.6um")
+
+via4.not(m5).output("m5.via4", "m5.via4 : m5 must enclose via4")
+m5.enclosing(via4, 0.31, euclidian).output("m5.3", "m4.3 : min. m5 enclosure of via4 : 0.31um")
+
+#   nsm
+nsm.width(3.0, euclidian).output("nsm.1", "nsm.1 : min. nsm width : 3.0um")
+nsm.isolated(4.0, euclidian).output("nsm.2", "nsm.2 : min. nsm spacing : 4.0um")
+nsm.enclosing(diff, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of diff : 3.0um")
+nsm.enclosing(tap, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of tap : 3.0um")
+nsm.enclosing(poly, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of poly : 3.0um")
+nsm.enclosing(li, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of li : 3.0um")
+nsm.enclosing(m1, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m1 : 3.0um")
+nsm.enclosing(m2, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m2 : 3.0um")
+nsm.enclosing(m3, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m3 : 3.0um")
+nsm.enclosing(m4, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m4 : 3.0um")
+nsm.enclosing(m5, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of m5 : 3.0um")
+nsm.enclosing(cfom, 3.0, euclidian).output("nsm.4", "nsm.4 : min. nsm enclosure of cfom : 3.0um")
+if backend_flow = AL
+  nsm.separation(diff, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to diff : 1.0um")
+  nsm.separation(tap, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to tap : 1.0um")
+  nsm.separation(poly, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to poly : 1.0um")
+  nsm.separation(li, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to li : 1.0um")
+  nsm.separation(m1, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m1 : 1.0um")
+  nsm.separation(m2, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m2 : 1.0um")
+  nsm.separation(m3, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m3 : 1.0um")
+  nsm.separation(m4, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m4 : 1.0um")
+  nsm.separation(m5, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to m5 : 1.0um")
+  nsm.separation(cfom, 1.0, euclidian).output("nsm.3", "nsm.3 : min. nsm spacing to cfom : 1.0um")
+end
+
+#   pad
+pad.isolated(1.27, euclidian).output("pad.2", "pad.2 : min. pad spacing : 1.27um")
+
+end #BEOL
+
+if FEOL
+info("FEOL section")
+
+#   mf
+mf.not_interacting(mf.edges.without_length(0.8)).output("mf.1", "mf.1 : minimum/maximum width of fuse : 0.8um")
+mf.not_interacting(mf.edges.without_length(7.2)).output("mf.2", "mf.2 : minimum/maximum length of fuse : 7.2um")
+mf.isolated(1.96, euclidian).output("mf.3", "mf.3 : min. fuse center spacing : 2.76um")
+# fuses need more clarification on fuse_shield, fuse layers ...
+
+#   hvi
+hvi.width(0.6, euclidian).output("hvi.1", "hvi.1 : min. hvi width : 0.6um")
+hvi.isolated(0.7, euclidian).output("hvi.2", "hvi.2 : min. hvi spacing, merge if less : 0.7um")
+hvi.and(tunm).output("hvi.4", "hvi.4 : hvi must not overlapp tunm")
+hvi.and(nwell).separation(nwell, 2.0, euclidian).output("hvnwell.8", "hvnwelli.8 : min. hvnwel spacing to nwell : 2.0")
+areaid_hl.not(hvi).output("hvnwel.9", "hvnwell.9 : hvi must overlapp hvnwell")
+# rule hvnell.10 not coded
+diff.not(psdm.and(diff_rs)).and(hvi).width(0.29, euclidian).output("hvdifftap.14", "hvdifftap.14 : min. diff inside hvi width : 0.29um")
+diff.and(psdm.and(diff_rs)).and(hvi).width(0.15, euclidian).output("hvdifftap.14a", "hvdifftap.14a : min. p+diff resistor inside hvi width : 0.15um")
+diff.and(hvi).isolated(0.3, euclidian).output("hvdifftap.15a", "hvdifftap.15a : min. diff inside hvi spacing : 0.3um")
+diff.and(hvi).and(nsdm).separation(diff.and(hvi).and(psdm), 0.37, euclidian).polygons.without_area(0).output("hvdifftap.15b", "hvdifftap.15b : min. n+diff inside hvi spacing to p+diff inside hvi except abutting: 0.37um")
+tap.and(hvi).edges.and(diff).without_length(0.7).output("hvdifftap.16", "hvdifftap.16 : min. tap inside hvi abuttng diff : 0.7um")
+hvi.and(nwell).enclosing(diff, 0.33, euclidian).output("hvdifftap.17", "hvdifftap.17 : min. hvnwell enclosure of p+diff : 0.33um")
+hvi.and(nwell).separation(diff, 0.43, euclidian).output("hvdifftap.18", "hvdifftap.18 : min. hvnwell spacing to n+diff : 0.43um")
+hvi.and(nwell).enclosing(tap, 0.33, euclidian).output("hvdifftap.19", "hvdifftap.19 : min. hvnwell enclosure of n+tap : 0.33um")
+hvi.and(nwell).separation(tap, 0.43, euclidian).output("hvdifftap.20", "hvdifftap.20 : min. hvnwell spacing to p+tap : 0.43um")
+hvi.and(diff).edges.not(diff.edges).output("hvdifftap.21", "hvdifftap.21 : diff must not straddle hvi")
+hvi.and(tap).edges.not(tap.edges).output("hvdifftap.21", "hvdifftap.21 : tap must not straddle hvi")
+hvi.enclosing(difftap, 0.18, euclidian).output("hvdifftap.22", "hvdifftap.22 : min. hvi enclosure of diff or tap : 0.18um")
+hvi.separation(difftap, 0.18, euclidian).output("hvdifftap.23", "hvdifftap.23 : min. hvi spacing to diff or tap : 0.18um")
+hvi.and(diff).not(nwell).separation(nwell, 0.43, euclidian).output("hvdifftap.24", "hvdifftap.24 : min. hv n+diff spacing to nwell : 0.43um")
+diff.and(hvi).not(nwell).isolated(1.07, euclidian).polygons.and(tap).output("hvdifftap.25", "hvdifftap.25 : min. n+diff inside hvi spacing accros p+tap  : 1.07um")
+diff.not(poly).edges.and(gate.and(hvi).edges).space(0.35, euclidian).output("hvpoly.13", "hvpoly.13: min. hvi gate length : 0.5um")
+hvi.and(poly).edges.not(poly.edges).output("hvpoly.14", "hvpoly.14 : poly must not straddle hvi")
+
+#   hvntm
+hvntm.width(0.7, euclidian).output("hvntm.1", "hvntm.1 : min. hvntm width : 0.7um")
+hvntm.isolated(0.7, euclidian).output("hvntm.2", "hvntm.2 : min. hvntm spacing : 0.7um")
+hvntm.enclosing(diff.and(nwell).and(hvi), 0.185, euclidian).output("hvntm.3", "hvntm.3 : min. hvntm enclosure of hv n+diff : 0.185um")
+hvntm.separation(diff.not(nwell).not(hvi), 0.185, euclidian).output("hvntm.4", "hvntm.4 : min. hvntm spacing to n+diff : 0.185um")
+hvntm.separation(diff.and(nwell).not(hvi), 0.185, euclidian).output("hvntm.5", "hvntm.5 : min. hvntm spacing to p+diff : 0.185um")
+hvntm.separation(tap.not(nwell).not(hvi), 0.185, euclidian).polygons.without_area(0).output("hvntm.6a", "hvntm.6a : min. hvntm spacing to p+tap : 0.185um")
+hvntm.and(areaid_ce).output("hvntm.9", "hvntm.9 : hvntm must not overlapp areaid.ce")
+
+#   denmos
+poly.not_interacting(pwde).interacting(areaid_en).width(1.055, projection).output("denmos.1", "denmos.1 : min. de_nfet gate width : 1.055um")
+diff.not_interacting(pwde).enclosing(poly.interacting(areaid_en), 0.28, projection).polygons.without_area(0).output("denmos.2", "denmos.2 : min. de_nfet source ouside poly width : 0.28um")
+diff.not_interacting(pwde).and(poly.interacting(areaid_en)).width(0.925, projection).output("denmos.3", "denmos.3 : min. de_nfet source inside poly width : 0.925um")
+diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).width(0.17, euclidian).output("denmos.4", "denmos.4 : min. de_nfet drain width : 0.17um")
+nwell.not_interacting(pwde).and(poly.interacting(areaid_en)).width(0.225, projection).polygons.or(nwell.and(poly.interacting(areaid_en)).sized(-0.1125).sized(0.1125)).output("denmos.5", "denmos.5 : min. de_nfet source inside nwell width : 0.225m")
+diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).separation(diff.interacting(poly.interacting(areaid_en)), 1.585, projection).output("denmos.6", "denmos.6 : min. de_nfet source spacing to drain : 1.585um")
+nwell.not_interacting(pwde).and(poly.and(diff).interacting(areaid_en)).edges.without_length(5.0, nil).output("denmos.7", "denmos.7 : min. de_nfet channel width : 5.0um")
+diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("denmos.8", "denmos.8 : 90deg. not allowed for de_nfet drain")
+nwell.not_interacting(pwde).interacting(areaid_en).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("denmos.9a", "denmos.9a : 90deg. not allowed for de_nfet nwell")
+nwell.not_interacting(pwde).interacting(areaid_en).edges.with_angle(45).without_length(0.607..0.609).output("denmos.9a", "denmos.9a : 45deg. bevels of de_nfet nwell should be 0.43um from corners")
+nwell.not_interacting(pwde).interacting(areaid_en).edges.with_angle(135).without_length(0.607..0.609).output("denmos.9a", "denmos.9a : 45deg. bevels of de_nfet nwell should be 0.43um from corners")
+diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(45).without_length(0.7..0.71).output("denmos.9b", "denmos.9b : 45deg. bevels of de_nfet drain should be 0.05um from corners")
+diff.not_interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(135).without_length(0.7..0.71).output("denmos.9b", "denmos.9b : 45deg. bevels of de_nfet drain should be 0.05um from corners")
+nwell.not_interacting(pwde).enclosing(diff.interacting(areaid_en).not_interacting(poly), 0.66, euclidian).output("denmos.10", "denmos.10 : min. nwell enclosure of de_nfet drain : 0.66um")
+nwell.not_interacting(pwde).interacting(areaid_en).separation(tap.not(nwell), 0.86, euclidian).output("denmos.11", "denmos.11 : min. de_nfet nwell spacing to tap : 0.86um")
+nwell.not_interacting(pwde).interacting(areaid_en).isolated(2.4, euclidian).output("denmos.12", "denmos.12 : min. de_nfet nwell : 2.4um")
+nsdm.not_interacting(pwde).enclosing(diff.interacting(areaid_en).interacting(poly), 0.13, euclidian).output("denmos.13", "denmos.13 : min. nsdm enclosure of de_nfet source : 0.13um")
+
+#   depmos
+poly.interacting(pwde).interacting(areaid_en).width(1.05, projection).output("depmos.1", "depmos.1 : min. de_pfet gate width : 1.05um")
+diff.interacting(pwde).enclosing(poly.interacting(areaid_en), 0.28, projection).polygons.without_area(0).output("depmos.2", "depmos.2 : min. de_pfet source ouside poly width : 0.28um")
+diff.interacting(pwde).and(poly.interacting(areaid_en)).width(0.92, projection).output("depmos.3", "depmos.3 : min. de_pfet source inside poly width : 0.92um")
+diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).width(0.17, euclidian).output("depmos.4", "depmos.4 : min. de_pfet drain width : 0.17um")
+pwde.not(nwell).and(poly.interacting(areaid_en)).width(0.26, projection).polygons.or(pwde.not(nwell).and(poly.interacting(areaid_en)).sized(-0.13).sized(0.13)).output("depmos.5", "depmos.5 : min. de_pfet source inside nwell width : 0.26m")
+diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).separation(diff.interacting(poly.interacting(areaid_en)), 1.19, projection).output("depmos.6", "depmos.6 : min. de_pfet source spacing to drain : 1.19um")
+nwell.interacting(pwde).and(poly.and(diff).interacting(areaid_en)).edges.without_length(5.0, nil).output("depmos.7", "depmos.7 : min. de_pfet channel width : 5.0um")
+diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("depmos.8", "depmos.8 : 90deg. not allowed for de_pfet drain")
+pwde.not(nwell).interacting(areaid_en).edges.without_angle(45).without_angle(135).without_angle(225).without_angle(315).output("depmos.9a", "depmos.9a : 90deg. not allowed for de_pfet pwell")
+pwde.not(nwell).interacting(areaid_en).edges.with_angle(45).without_length(0.607..0.609).output("depmos.9a", "depmos.9a : 45deg. bevels of de_pfet pwell should be 0.43um from corners")
+pwde.not(nwell).interacting(areaid_en).edges.with_angle(135).without_length(0.607..0.609).output("depmos.9a", "depmos.9a : 45deg. bevels of de_pfet pwell should be 0.43um from corners")
+diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(45).without_length(0.7..0.71).output("depmos.9b", "depmos.9b : 45deg. bevels of de_pfet drain should be 0.05um from corners")
+diff.interacting(pwde).interacting(areaid_en).not_interacting(poly).edges.with_angle(135).without_length(0.7..0.71).output("depmos.9b", "depmos.9b : 45deg. bevels of de_pfet drain should be 0.05um from corners")
+nwell.interacting(pwde).separation(diff.interacting(areaid_en).not_interacting(poly), 0.86, euclidian).output("depmos.10", "depmos.10 : min. pwell enclosure of de_pfet drain : 0.86um")
+pwde.not(nwell).interacting(areaid_en).separation(tap.and(nwell), 0.66, euclidian).output("depmos.11", "depmos.11 : min. de_pfet pwell spacing to tap : 0.66um")
+psdm.interacting(pwde).enclosing(diff.interacting(areaid_en).interacting(poly), 0.13, euclidian).output("depmos.12", "depmos.12 : min. psdm enclosure of de_pfet source : 0.13um")
+
+#   extd
+areaid_en.and(difftap).edges.not(difftap.edges).output("extd.1", "extd.1 : difftap must not straddle areaid.en")
+difftap.interacting(areaid_en).not(poly).with_area(0).output("extd.2", "extd.2 : poly must not overlapp entirely difftap in areaid.en")
+# rules extd.4, extd.5, extd.6, extd.7 not coded because specific to some cells
+
+#   vhvi
+# rules vhvi.vhv.1, vhvi.vhv.2, vhvi.vhv.3, vhvi.vhv.4, vhvi.vhv.5, vhvi.vhv.6 not coded
+vhvi.width(0.02, euclidian).output("vhvi.1", "vhvi.1 : min. vhvi width : 0.02um")
+vhvi.and(areaid_ce).output("vhvi.2", "vhvi.2 : vhvi must not overlap areaid.ce")
+vhvi.and(hvi).output("vhvi.3", "vhvi.3 : vhvi must not overlap hvi")
+# rules vhvi.4, vhvi.6 not coded
+vhvi.and(diff).edges.not(diff.edges).output("vhvi.5", "vhvi.5 : vhvi must not straddle diff")
+vhvi.and(tap).edges.not(tap.edges).output("vhvi.5", "vhvi.5 : vhvi must not straddle tap")
+vhvi.and(poly).edges.not(poly.edges).output("vhvi.7", "vhvi.7 : vhvi must not straddle poly")
+
+nwell.and(vhvi).separation(nwell, 2.5, euclidian).output("hv.nwell.1", "hv.nwell.1 : min. vhvi nwell spacing to nwell : 2.5um")
+diff.and(vhvi).isolated(0.3, euclidian).output("hv.diff.1", "hv.diff.1 : min. vhvi diff spacing : 0.3um")
+nwell.interacting(diff.and(vhvi)).separation(diff.not(nwell), 0.43, euclidian).output("hv.diff.2", "hv.diff.2 : min. vhvi nwell spacing n+diff : 0.43um")
+diff.and(vhvi).not(nwell).separation(nwell, 0.55, euclidian).output("hv.diff.3a", "hv.diff.3a : min. vhvi n+diff spacing nwell : 0.55um")
+# rule hv.diff.3b not coded
+poly.and(vhvi).not(diff).separation(diff, 0.3, euclidian).polygons.without_area(0).output("hv.poly.2", "hv.poly.2 : min. vhvi poly spacing to diff : 0.3um")
+poly.and(vhvi).not(diff).separation(nwell, 0.55, euclidian).polygons.without_area(0).output("hv.poly.3", "hv.poly.3 : min. vhvi poly spacing to nwell : 0.55um")
+nwell.enclosing(poly.and(vhvi).not(diff), 0.3, euclidian).polygons.without_area(0).output("hv.poly.4", "hv.poly.4 : min. nwell enclosure of vhvi poly : 0.3um")
+#poly.and(vhvi).enclosing(diff.interacting(areaid_en), 0.16, projection).polygons.without_area(0).output("hv.poly.6", "hv.poly.6 : min. poly enclosure of hvfet gate : 0.16um")
+# rule hv.poly.7 not coded
+
+#   uhvi
+uhvi.and(diff).edges.not(diff.edges).output("uhvi.1", "uhvi.1 : diff must not straddle uhvi")
+uhvi.and(tap).edges.not(tap.edges).output("uhvi.1", "uhvi.1 : tap must not straddle uhvi")
+uhvi.and(poly).edges.not(poly.edges).output("uhvi.2", "uhvi.2 : poly must not straddle uhvi")
+pwbm.not(uhvi).output("uhvi.3", "uhvi.3 : uhvi must not enclose pwbm")
+uhvi.and(dnwell).edges.not(dnwell.edges).output("uhvi.4", "uhvi.4 : dnwell must not straddle uhvi")
+areaid_en20.not(uhvi).output("uhvi.5", "uhvi.5 : uhvi must not enclose areaid.en20")
+#dnwell.not(uhvi).output("uhvi.6", "uhvi.6 : uhvi must not enclose dnwell")
+natfet.not(uhvi).output("uhvi.7", "uhvi.7 : uhvi must not enclose natfet")
+
+#   pwell_res
+pwell_rs.width(2.65).output("pwres.2", "pwres.2 : min. pwell resistor width : 2.65um")
+pwell_rs.sized(-2.65).sized(2.65).output("pwres.2", "pwres.2 : max. pwell resistor width : 2.65um")
+pwell_rs.interacting(pwell_rs.edges.with_length(2.651,26.499)).output("pwres.3", "pwres.3 : min. pwell resistor length : 26.5um")
+pwell_rs.interacting(pwell_rs.edges.with_length(265.0, nil)).output("pwres.4", "pwres.4 : max. pwell resistor length : 265um")
+tap.interacting(pwell_rs).separation(nwell, 0.22, euclidian).output("pwres.5", "pwres.5 : min. pwell resistor tap spacing to nwell : 0.22um")
+tap.interacting(pwell_rs).and(tap.sized(0.22).and(nwell)).output("pwres.5", "pwres.5 : max. pwell resistor tap spacing to nwell : 0.22um")
+tap.interacting(pwell_rs).width(0.53).output("pwres.6", "pwres.6 : min. width of tap inside pwell resistor : 0.53um")
+tap.interacting(pwell_rs).sized(-0.265).sized(0.265).output("pwres.6", "pwres.6 : max. width of tap inside pwell resistor : 0.53um")
+# rules pwres.7a, pwres.7b not coded
+pwell_rs.and(diff).output("pwres.8", "pwres.8 : diff not allowed inside pwell resistor")
+pwell_rs.and(poly).output("pwres.8", "pwres.8 : poly not allowed inside pwell resistor")
+# rules pwres.9, pwres.10 not coded
+
+#   rf_diode
+areaid_re.with_angle(0 .. 90).output("rfdiode.1", "rfdiode.1 : non 90 degree angle areaid.re")
+areaid_re.not(nwell).or(nwell.interacting(areaid_re).not(areaid_re)).output("rfdiode.2", "rfdiode.2 : areaid.re must coincide rf nwell diode")
+# rule rfdiode.3 not coded
+
+end #FEOL
+
+if OFFGRID
+info("OFFGRID-ANGLES section")
+
+dnwell.ongrid(0.005).output("dnwell_OFFGRID", "x.1b : OFFGRID vertex on dnwell")
+dnwell.with_angle(0 .. 45).output("dnwell_angle", "x.3a : non 45 degree angle dnwell")
+nwell.ongrid(0.005).output("nwell_OFFGRID", "x.1b : OFFGRID vertex on nwell")
+nwell.with_angle(0 .. 45).output("nwell_angle", "x.3a : non 45 degree angle nwell")
+pwbm.ongrid(0.005).output("pwbm_OFFGRID", "x.1b : OFFGRID vertex on pwbm")
+pwbm.with_angle(0 .. 45).output("pwbm_angle", "x.3a : non 45 degree angle pwbm")
+pwde.ongrid(0.005).output("pwde_OFFGRID", "x.1b : OFFGRID vertex on pwde")
+pwde.with_angle(0 .. 45).output("pwde_angle", "x.3a : non 45 degree angle pwde")
+hvtp.ongrid(0.005).output("hvtp_OFFGRID", "x.1b : OFFGRID vertex on hvtp")
+hvtp.with_angle(0 .. 45).output("hvtp_angle", "x.3a : non 45 degree angle hvtp")
+hvtr.ongrid(0.005).output("hvtr_OFFGRID", "x.1b : OFFGRID vertex on hvtr")
+hvtr.with_angle(0 .. 45).output("hvtr_angle", "x.3a : non 45 degree angle hvtr")
+lvtn.ongrid(0.005).output("lvtn_OFFGRID", "x.1b : OFFGRID vertex on lvtn")
+lvtn.with_angle(0 .. 45).output("lvtn_angle", "x.3a : non 45 degree angle lvtn")
+ncm.ongrid(0.005).output("ncm_OFFGRID", "x.1b : OFFGRID vertex on ncm")
+ncm.with_angle(0 .. 45).output("ncm_angle", "x.3a : non 45 degree angle ncm")
+diff.ongrid(0.005).output("diff_OFFGRID", "x.1b : OFFGRID vertex on diff")
+tap.ongrid(0.005).output("tap_OFFGRID", "x.1b : OFFGRID vertex on tap")
+diff.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("diff_angle", "x.2 : non 90 degree angle diff")
+diff.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("diff_angle", "x.2c : non 45 degree angle diff")
+tap.not(areaid_en.and(uhvi)).with_angle(0 .. 90).output("tap_angle", "x.2 : non 90 degree angle tap")
+tap.and(areaid_en.and(uhvi)).with_angle(0 .. 45).output("tap_angle", "x.2c : non 45 degree angle tap")
+tunm.ongrid(0.005).output("tunm_OFFGRID", "x.1b : OFFGRID vertex on tunm")
+tunm.with_angle(0 .. 45).output("tunm_angle", "x.3a : non 45 degree angle tunm")
+poly.ongrid(0.005).output("poly_OFFGRID", "x.1b : OFFGRID vertex on poly")
+poly.with_angle(0 .. 90).output("poly_angle", "x.2 : non 90 degree angle poly")
+rpm.ongrid(0.005).output("rpm_OFFGRID", "x.1b : OFFGRID vertex on rpm")
+rpm.with_angle(0 .. 45).output("rpm_angle", "x.3a : non 45 degree angle rpm")
+npc.ongrid(0.005).output("npc_OFFGRID", "x.1b : OFFGRID vertex on npc")
+npc.with_angle(0 .. 45).output("npc_angle", "x.3a : non 45 degree angle npc")
+nsdm.ongrid(0.005).output("nsdm_OFFGRID", "x.1b : OFFGRID vertex on nsdm")
+nsdm.with_angle(0 .. 45).output("nsdm_angle", "x.3a : non 45 degree angle nsdm")
+psdm.ongrid(0.005).output("psdm_OFFGRID", "x.1b : OFFGRID vertex on psdm")
+psdm.with_angle(0 .. 45).output("psdm_angle", "x.3a : non 45 degree angle psdm")
+licon.ongrid(0.005).output("licon_OFFGRID", "x.1b : OFFGRID vertex on licon")
+licon.with_angle(0 .. 90).output("licon_angle", "x.2 : non 90 degree angle licon")
+li.ongrid(0.005).output("li_OFFGRID", "x.1b : OFFGRID vertex on li")
+li.with_angle(0 .. 45).output("li_angle", "x.3a : non 45 degree angle li")
+mcon.ongrid(0.005).output("ct_OFFGRID", "x.1b : OFFGRID vertex on mcon")
+mcon.with_angle(0 .. 90).output("ct_angle", "x.2 : non 90 degree angle mcon")
+vpp.ongrid(0.005).output("vpp_OFFGRID", "x.1b : OFFGRID vertex on vpp")
+vpp.with_angle(0 .. 45).output("vpp_angle", "x.3a : non 45 degree angle vpp")
+m1.ongrid(0.005).output("m1_OFFGRID", "x.1b : OFFGRID vertex on m1")
+m1.with_angle(0 .. 45).output("m1_angle", "x.3a : non 45 degree angle m1")
+via.ongrid(0.005).output("via_OFFGRID", "x.1b : OFFGRID vertex on via")
+via.with_angle(0 .. 90).output("via_angle", "x.2 : non 90 degree angle via")
+m2.ongrid(0.005).output("m2_OFFGRID", "x.1b : OFFGRID vertex on m2")
+m2.with_angle(0 .. 45).output("m2_angle", "x.3a : non 45 degree angle m2")
+via2.ongrid(0.005).output("via2_OFFGRID", "x.1b : OFFGRID vertex on via2")
+via2.with_angle(0 .. 90).output("via2_angle", "x.2 : non 90 degree angle via2")
+m3.ongrid(0.005).output("m3_OFFGRID", "x.1b : OFFGRID vertex on m3")
+m3.with_angle(0 .. 45).output("m3_angle", "x.3a : non 45 degree angle m3")
+via3.ongrid(0.005).output("via3_OFFGRID", "x.1b : OFFGRID vertex on via3")
+via3.with_angle(0 .. 90).output("via3_angle", "x.2 : non 90 degree angle via3")
+nsm.ongrid(0.005).output("nsm_OFFGRID", "x.1b : OFFGRID vertex on nsm")
+nsm.with_angle(0 .. 45).output("nsm_angle", "x.3a : non 45 degree angle nsm")
+m4.ongrid(0.005).output("m4_OFFGRID", "x.1b : OFFGRID vertex on m4")
+m4.with_angle(0 .. 45).output("m4_angle", "x.3a : non 45 degree angle m4")
+via4.ongrid(0.005).output("via4_OFFGRID", "x.1b : OFFGRID vertex on via4")
+via4.with_angle(0 .. 90).output("via4_angle", "x.2 : non 90 degree angle via4")
+m5.ongrid(0.005).output("m5_OFFGRID", "x.1b : OFFGRID vertex on m5")
+m5.with_angle(0 .. 45).output("m5_angle", "x.3a : non 45 degree angle m5")
+pad.ongrid(0.005).output("pad_OFFGRID", "x.1b : OFFGRID vertex on pad")
+pad.with_angle(0 .. 45).output("pad_angle", "x.3a : non 45 degree angle pad")
+mf.ongrid(0.005).output("mf_OFFGRID", "x.1b : OFFGRID vertex on mf")
+mf.with_angle(0 .. 90).output("mf_angle", "x.2 : non 90 degree angle mf")
+hvi.ongrid(0.005).output("hvi_OFFGRID", "x.1b : OFFGRID vertex on hvi")
+hvi.with_angle(0 .. 45).output("hvi_angle", "x.3a : non 45 degree angle hvi")
+hvntm.ongrid(0.005).output("hvntm_OFFGRID", "x.1b : OFFGRID vertex on hvntm")
+hvntm.with_angle(0 .. 45).output("hvntm_angle", "x.3a : non 45 degree angle hvntm")
+vhvi.ongrid(0.005).output("vhvi_OFFGRID", "x.1b : OFFGRID vertex on vhvi")
+vhvi.with_angle(0 .. 45).output("vhvi_angle", "x.3a : non 45 degree angle vhvi")
+uhvi.ongrid(0.005).output("uhvi_OFFGRID", "x.1b : OFFGRID vertex on uhvi")
+uhvi.with_angle(0 .. 45).output("uhvi_angle", "x.3a : non 45 degree angle uhvi")
+pwell_rs.ongrid(0.005).output("pwell_rs_OFFGRID", "x.1b : OFFGRID vertex on pwell_rs")
+pwell_rs.with_angle(0 .. 45).output("pwell_rs_angle", "x.3a : non 45 degree angle pwell_rs")
+areaid_re.ongrid(0.005).output("areaid_re_OFFGRID", "x.1b : OFFGRID vertex on areaid.re")
+
+end #OFFGRID</text>
+</klayout-macro>

alu_w4_2ops_sky130_50mhz/flow/drc_report.rpt

@@ -0,0 +1,892 @@
+<?xml version="1.0" encoding="utf-8"?>
+<report-database>
+ <description>SKY130 DRC runset</description>
+ <original-file/>
+ <generator>drc: script='/tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/drc_deck_patched.lydrc'</generator>
+ <top-cell>alu_w4_2ops</top-cell>
+ <tags>
+ </tags>
+ <categories>
+  <category>
+   <name>li.1</name>
+   <description>li.1 : min. li width : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.1a</name>
+   <description>li.1a : min. li width for the cells s8rf2_xcmvpp_hd5_* : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3</name>
+   <description>li.3 : min. li spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.3a</name>
+   <description>li.3a : min. li spacing for the cells s8rf2_xcmvpp_hd5_* : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.5</name>
+   <description>li.5 : min. li enclosure of licon of 2 opposite edges : 0.08um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li.6</name>
+   <description>li.6 : min. li area : 0.0561um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.1</name>
+   <description>ct.1 : minimum/maximum width of mcon : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.2</name>
+   <description>ct.2 : min. mcon spacing : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct.4</name>
+   <description>ct.4 : mcon should covered by li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.1</name>
+   <description>m1.1 : min. m1 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.2</name>
+   <description>m1.2 : min. m1 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.3ab</name>
+   <description>m1.3ab : min. 3um.m1 spacing m1 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4</name>
+   <description>m1.4 : min. m1 enclosure of mcon : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.4a</name>
+   <description>m1.4a : min. m1 enclosure of mcon for specific cells : 0.005um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.6</name>
+   <description>m1.6 : min. m1 area : 0.083um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.7</name>
+   <description>m1.7 : min. m1 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1.5</name>
+   <description>m1.5 : min. m1 enclosure of mcon of 2 opposite edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4c.5c</name>
+   <description>via.4c.5c : m1 must enclose all via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1a</name>
+   <description>via.1a : minimum/maximum width of via : 0.15um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.1b</name>
+   <description>via.1b : minimum/maximum width of via in areaid.mt: 0.15um or 0.23um or 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.2</name>
+   <description>via.2 : min. via spacing : 0.17um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4a</name>
+   <description>via.4a : min. m1 enclosure of 0.15um via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via.4b</name>
+   <description>via.4b : min. m1 enclosure of 0.23um via : 0.03um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via1.5a</name>
+   <description>via1.5a : min. m1 enclosure of 0.15um via of 2 opposite edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via1.5b</name>
+   <description>via1.5b : min. m1 enclosure of 0.23um via of 2 opposite edges : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.1</name>
+   <description>m2.1 : min. m2 width : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.2</name>
+   <description>m2.2 : min. m2 spacing : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.3ab</name>
+   <description>m2.3ab : min. 3um.m2 spacing m2 : 0.28um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.6</name>
+   <description>m2.6 : min. m2 area : 0.0676um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.7</name>
+   <description>m2.7 : min. m2 holes area : 0.14um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.via</name>
+   <description>m2.via : m2 must enclose via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.4</name>
+   <description>m2.4 : min. m2 enclosure of via : 0.055um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2.5</name>
+   <description>m2.5 : min. m2 enclosure of via of 2 opposite edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2</name>
+   <description>via2 : m2 must enclose all via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1a</name>
+   <description>via2.1a : minimum/maximum width of via2 : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.1b</name>
+   <description>via2.1b : minimum/maximum width of via2 in areaid.mt: 0.2um or 1.2um or 1.5um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.2</name>
+   <description>via2.2 : min. via2 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4</name>
+   <description>via2.4 : min. m2 enclosure of via2 : 0.04um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.4a</name>
+   <description>via2.4a : min. m2 enclosure of 1.5um via2 : 0.14um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2.5</name>
+   <description>via2.5 : min. m2 enclosure of via2 of 2 opposite edges : 0.085um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.1</name>
+   <description>m3.1 : min. m3 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.2</name>
+   <description>m3.2 : min. m3 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.3ab</name>
+   <description>m3.3ab : min. 3um.m3 spacing m3 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.6</name>
+   <description>m3.6 : min. m3 area : 0.24um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.via2</name>
+   <description>m3.via2 : m3 must enclose via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3.4</name>
+   <description>m3.4 : min. m3 enclosure of via2 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3</name>
+   <description>via3 : m3 must enclose all via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.1a</name>
+   <description>via3.1a : minimum/maximum width of via3 in areaid.mt: 0.2um or 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.2</name>
+   <description>via3.2 : min. via3 spacing : 0.2um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.4</name>
+   <description>via3.4 : min. m3 enclosure of via3 : 0.06um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3.5</name>
+   <description>via3.5 : min. m2 enclosure of via3 of 2 opposite edges : 0.09um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.1</name>
+   <description>m4.1 : min. m4 width : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.2</name>
+   <description>m4.2 : min. m4 spacing : 0.3um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.5ab</name>
+   <description>m4.5ab : min. 3um.m4 spacing m4 : 0.4um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.4</name>
+   <description>m4.4 : min. m4 area : 0.24um²</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.via3</name>
+   <description>m4.via3 : m4 must enclose via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m4.3</name>
+   <description>m4.3 : min. m4 enclosure of via3 : 0.065um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.1a</name>
+   <description>via4.1a : minimum/maximum width of via4 : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.2</name>
+   <description>via4.2 : min. via4 spacing : 0.8um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4.4</name>
+   <description>via4.4 : min. m4 enclosure of via4 : 0.19um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via4</name>
+   <description>via4 : m4 must enclose all via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.1</name>
+   <description>m5.1 : min. m5 width : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.2</name>
+   <description>m5.2 : min. m5 spacing : 1.6um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.via4</name>
+   <description>m5.via4 : m5 must enclose via4</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m5.3</name>
+   <description>m4.3 : min. m5 enclosure of via4 : 0.31um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.1</name>
+   <description>nsm.1 : min. nsm width : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.2</name>
+   <description>nsm.2 : min. nsm spacing : 4.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.4</name>
+   <description>nsm.4 : min. nsm enclosure of cfom : 3.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsm.3</name>
+   <description>nsm.3 : min. nsm spacing to cfom : 1.0um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pad.2</name>
+   <description>pad.2 : min. pad spacing : 1.27um</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>dnwell_angle</name>
+   <description>x.3a : non 45 degree angle dnwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nwell_angle</name>
+   <description>x.3a : non 45 degree angle nwell</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwbm_angle</name>
+   <description>x.3a : non 45 degree angle pwbm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwde_angle</name>
+   <description>x.3a : non 45 degree angle pwde</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtp_angle</name>
+   <description>x.3a : non 45 degree angle hvtp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>hvtr_angle</name>
+   <description>x.3a : non 45 degree angle hvtr</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>lvtn_angle</name>
+   <description>x.3a : non 45 degree angle lvtn</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ncm_angle</name>
+   <description>x.3a : non 45 degree angle ncm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>diff_angle</name>
+   <description>x.2c : non 45 degree angle diff</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tap_angle</name>
+   <description>x.2c : non 45 degree angle tap</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>tunm_angle</name>
+   <description>x.3a : non 45 degree angle tunm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>poly_angle</name>
+   <description>x.2 : non 90 degree angle poly</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>rpm_angle</name>
+   <description>x.3a : non 45 degree angle rpm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>npc_angle</name>
+   <description>x.3a : non 45 degree angle npc</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>nsdm_angle</name>
+   <description>x.3a : non 45 degree angle nsdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>psdm_angle</name>
+   <description>x.3a : non 45 degree angle psdm</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>licon_angle</name>
+   <description>x.2 : non 90 degree angle licon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>li_angle</name>
+   <description>x.3a : non 45 degree angle li</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>ct_angle</name>
+   <description>x.2 : non 90 degree angle mcon</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vpp_angle</name>
+   <description>x.3a : non 45 degree angle vpp</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m1</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m1_angle</name>
+   <description>x.3a : non 45 degree angle m1</description>
+   <categories>
+   </categories>
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+   <categories>
+   </categories>
+  </category>
+  <category>
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+   <description>x.2 : non 90 degree angle via</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m2_angle</name>
+   <description>x.3a : non 45 degree angle m2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via2_angle</name>
+   <description>x.2 : non 90 degree angle via2</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
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+   <description>x.1b : OFFGRID vertex on m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>m3_angle</name>
+   <description>x.3a : non 45 degree angle m3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on via3</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>via3_angle</name>
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+   <categories>
+   </categories>
+  </category>
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+   <categories>
+   </categories>
+  </category>
+  <category>
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+   <categories>
+   </categories>
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+  <category>
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+   <categories>
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+   <description>x.1b : OFFGRID vertex on via4</description>
+   <categories>
+   </categories>
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+   <categories>
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+  <category>
+   <name>m5_angle</name>
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+   <categories>
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+  </category>
+  <category>
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+   <categories>
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+   <categories>
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+  </category>
+  <category>
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+   <categories>
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+   <categories>
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+   <name>hvntm_angle</name>
+   <description>x.3a : non 45 degree angle hvntm</description>
+   <categories>
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+   <description>x.1b : OFFGRID vertex on vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>vhvi_angle</name>
+   <description>x.3a : non 45 degree angle vhvi</description>
+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>uhvi_OFFGRID</name>
+   <description>x.1b : OFFGRID vertex on uhvi</description>
+   <categories>
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+  </category>
+  <category>
+   <name>uhvi_angle</name>
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+  <category>
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+   <categories>
+   </categories>
+  </category>
+  <category>
+   <name>pwell_rs_angle</name>
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+   <categories>
+   </categories>
+  </category>
+  <category>
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+   <description>x.1b : OFFGRID vertex on areaid.re</description>
+   <categories>
+   </categories>
+  </category>
+ </categories>
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+   <variant/>
+   <layout-name/>
+   <references>
+   </references>
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+ <items>
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alu_w4_2ops_sky130_50mhz/flow/extracted/deepgate.json

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alu_w4_2ops_sky130_50mhz/flow/extracted/drc_labels.json

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+[{"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "violation_type": "clean", "violation_count": 0}]

alu_w4_2ops_sky130_50mhz/flow/extracted/geometry_patches.json

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alu_w4_2ops_sky130_50mhz/flow/extracted/mesoscale_blocks.json

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alu_w4_2ops_sky130_50mhz/flow/extracted/pin_access.json

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+[{"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "a[0]", "direction": "INPUT", "layer": "met3", "x": 400, "y": 18020}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "a[1]", "direction": "INPUT", "layer": "met3", "x": 400, "y": 9860}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "a[2]", "direction": "INPUT", "layer": "met3", "x": 400, "y": 11220}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "a[3]", "direction": "INPUT", "layer": "met3", "x": 400, "y": 4420}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "b[0]", "direction": "INPUT", "layer": "met3", "x": 400, "y": 1700}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "b[1]", "direction": "INPUT", "layer": "met3", "x": 400, "y": 12580}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "b[2]", "direction": "INPUT", "layer": "met3", "x": 400, "y": 15300}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "b[3]", "direction": "INPUT", "layer": "met3", "x": 400, "y": 7140}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "result[0]", "direction": "OUTPUT", "layer": "met3", "x": 400, "y": 16660}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "result[1]", "direction": "OUTPUT", "layer": "met3", "x": 400, "y": 5780}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "result[2]", "direction": "OUTPUT", "layer": "met3", "x": 400, "y": 13940}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "result[3]", "direction": "OUTPUT", "layer": "met3", "x": 400, "y": 3060}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "pin_name": "sel", "direction": "INPUT", "layer": "met3", "x": 400, "y": 8500}]

alu_w4_2ops_sky130_50mhz/flow/extracted/power_grid.json

@@ -0,0 +1 @@
+[]

alu_w4_2ops_sky130_50mhz/flow/extracted/timing_contexts.json

@@ -0,0 +1 @@
+[{"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "freq_mhz": 50, "wns_ns": null, "tns_ns": null, "utilization": 0.86, "num_instances": 44, "area_um2": 194.0, "multi_corner": ["ff_n40C_1v95 (fast)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "tt_025C_1v80 (typical) WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "ss_n40C_1v40 (slow)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "ff_n40C_1v95 (fast)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "tt_025C_1v80 (typical) WNS: NaN ns  TNS: NaN ns  [VIOLATED]", "ss_n40C_1v40 (slow)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]"], "power_mw": null, "drc_clean": true, "lvs_clean": true}]

alu_w4_2ops_sky130_50mhz/flow/extracted/trajectory_snapshots.json

@@ -0,0 +1 @@
+[{"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "phase": 1, "label": "Step 1/3: Synthesis", "type": "phase_start"}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "phase": 1, "cells": 17, "type": "synth_result"}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "phase": 1, "duration_s": 0.5, "type": "phase_end"}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "phase": 2, "label": "Step 2/3: Place and Route", "type": "phase_start"}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "phase": 2, "instances": 44, "utilization": 0.86, "type": "pnr_result"}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "phase": 2, "duration_s": 7.0, "type": "phase_end"}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "phase": 3, "label": "Step 3/3: GDS Generation", "type": "phase_start"}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "phase": 3, "duration_s": 15.51, "type": "phase_end"}, {"run_id": "alu_w4_2ops_sky130_50mhz", "pdk": "sky130", "phase": 3, "signoff": "PASS", "type": "signoff_result"}]

alu_w4_2ops_sky130_50mhz/flow/flow_log.txt

@@ -0,0 +1,94 @@
+╔══════════════════════════════════════════╗
+║          Zyphar Flow v1.0.0              ║
+║    Complete RTL-to-GDSII Toolchain       ║
+╚══════════════════════════════════════════╝
+
+Configuration:
+  Input:     /tmp/datagen_designs/alu_w4_2ops/alu_w4_2ops.v
+  Top:       alu_w4_2ops
+  PDK:       Sky130
+  Frequency: 50 MHz
+  Clock:     clk
+  Output:    /tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow
+
+Starting flow...
+
+=== Step 1/3: Synthesis ===
+Synthesis complete: 17 cells, 0.00 um^2
+  Wires: 17, Modules: 1
+  Netlist: /tmp/zyphar_netlist_973323.v
+  Duration: 0.5s
+
+--- CDC Analysis ---
+  No clock domain crossings detected
+
+--- Native Re-Optimization ---
+  Skipped (no Liberty file provided, use --liberty)
+
+=== Step 2/3: Place and Route ===
+  Input netlist: /tmp/zyphar_netlist_973323.v
+  PDK: Sky130, Freq: 50 MHz, Clock: clk
+  Utilization: 45%, Aspect ratio: 1.0, Placement density: 0.80 (auto)
+  PDN: true, Detailed route: true, Fillers: true, Antenna: true
+PnR complete: 44 instances, 0.86 utilization
+  DEF: /tmp/zyphar_pnr_973323.def
+  WNS: N/A (combinational)
+  Duration: 7.0s
+
+--- Multi-Corner STA ---
+  Using post-PnR netlist with SPEF back-annotation
+  ff_n40C_1v95 (fast)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+  tt_025C_1v80 (typical) WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+  ss_n40C_1v40 (slow)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+
+--- Power Analysis ---
+  Power analysis skipped: No Liberty file available (use --liberty or set SKY130_LIBERTY)
+
+=== Step 3/3: GDS Generation ===
+GDS generation complete: /tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/alu_w4_2ops.gds
+
+=== Signoff Checks ===
+
+--- DRC ---
+  DRC: CLEAN
+
+--- LVS ---
+  LVS: CLEAN
+
+═══════════════════════════════════════════
+                  RESULTS                  
+═══════════════════════════════════════════
+
+Synthesis:
+  Cells:     17
+  Netlist:   /tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/netlist.v
+
+Place & Route:
+  DEF:       /tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/output.def
+  WNS:       N/A (combinational)
+  Util:      86.0%
+  Instances: 44
+  Area:      194.00 um^2
+
+GDSII:       /tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/alu_w4_2ops.gds
+
+Multi-Corner STA:
+  ff_n40C_1v95 (fast)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+  tt_025C_1v80 (typical) WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+  ss_n40C_1v40 (slow)  WNS: NaN ns  TNS: NaN ns  [VIOLATED]
+
+SPEF:        /tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/alu_w4_2ops.spef
+
+Duration:    15.51s
+
+Signoff:
+  Timing:         N/A (combinational)
+  DRC:            CLEAN
+  DRC report:     /tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/drc_report.rpt
+  LVS:            CLEAN
+  LVS report:     /tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/lvs_report.lyrdb
+
+  SIGNOFF: PASS
+
+Flow completed successfully!
+

alu_w4_2ops_sky130_50mhz/flow/klayout_lvs.log

@@ -0,0 +1,780 @@
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+"&" in: lvs_deck_patched.lylvs:132
+    Polygons (raw): 82 (flat)  40 (hierarchical)
+    Elapsed: 0.000s  Memory: 1175.00M
+"-" in: lvs_deck_patched.lylvs:133
+    Polygons (raw): 102 (flat)  52 (hierarchical)
+    Elapsed: 0.010s  Memory: 1155.00M
+"-" in: lvs_deck_patched.lylvs:134
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1165.00M
+"-" in: lvs_deck_patched.lylvs:134
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1135.00M
+"-" in: lvs_deck_patched.lylvs:134
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1135.00M
+"-" in: lvs_deck_patched.lylvs:135
+    Polygons (raw): 20 (flat)  10 (hierarchical)
+    Elapsed: 0.000s  Memory: 1136.00M
+"-" in: lvs_deck_patched.lylvs:135
+    Polygons (raw): 20 (flat)  10 (hierarchical)
+    Elapsed: 0.000s  Memory: 1136.00M
+"&" in: lvs_deck_patched.lylvs:135
+    Polygons (raw): 82 (flat)  40 (hierarchical)
+    Elapsed: 0.000s  Memory: 1156.00M
+"-" in: lvs_deck_patched.lylvs:136
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1176.00M
+"-" in: lvs_deck_patched.lylvs:136
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1136.00M
+"&" in: lvs_deck_patched.lylvs:136
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1136.00M
+"-" in: lvs_deck_patched.lylvs:138
+    Polygons (raw): 27 (flat)  12 (hierarchical)
+    Elapsed: 0.000s  Memory: 1156.00M
+"&" in: lvs_deck_patched.lylvs:138
+    Polygons (raw): 27 (flat)  12 (hierarchical)
+    Elapsed: 0.000s  Memory: 1176.00M
+"-" in: lvs_deck_patched.lylvs:139
+    Polygons (raw): 3 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 1166.00M
+"&" in: lvs_deck_patched.lylvs:139
+    Polygons (raw): 3 (flat)  1 (hierarchical)
+    Elapsed: 0.000s  Memory: 1166.00M
+"&" in: lvs_deck_patched.lylvs:140
+    Polygons (raw): 82 (flat)  40 (hierarchical)
+    Elapsed: 0.000s  Memory: 1176.00M
+"-" in: lvs_deck_patched.lylvs:141
+    Polygons (raw): 109 (flat)  52 (hierarchical)
+    Elapsed: 0.000s  Memory: 1156.00M
+"-" in: lvs_deck_patched.lylvs:142
+    Polygons (raw): 82 (flat)  40 (hierarchical)
+    Elapsed: 0.000s  Memory: 1136.00M
+"-" in: lvs_deck_patched.lylvs:142
+    Polygons (raw): 82 (flat)  40 (hierarchical)
+    Elapsed: 0.000s  Memory: 1137.00M
+"-" in: lvs_deck_patched.lylvs:142
+    Polygons (raw): 82 (flat)  40 (hierarchical)
+    Elapsed: 0.000s  Memory: 1137.00M
+"-" in: lvs_deck_patched.lylvs:143
+    Polygons (raw): 82 (flat)  40 (hierarchical)
+    Elapsed: 0.000s  Memory: 1137.00M
+"-" in: lvs_deck_patched.lylvs:143
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1137.00M
+"&" in: lvs_deck_patched.lylvs:143
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1137.00M
+"-" in: lvs_deck_patched.lylvs:144
+    Polygons (raw): 82 (flat)  40 (hierarchical)
+    Elapsed: 0.000s  Memory: 1137.00M
+"-" in: lvs_deck_patched.lylvs:144
+    Polygons (raw): 82 (flat)  40 (hierarchical)
+    Elapsed: 0.000s  Memory: 1137.00M
+"&" in: lvs_deck_patched.lylvs:144
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1137.00M
+"-" in: lvs_deck_patched.lylvs:145
+    Polygons (raw): 82 (flat)  40 (hierarchical)
+    Elapsed: 0.000s  Memory: 1137.00M
+"&" in: lvs_deck_patched.lylvs:145
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1137.00M
+"&" in: lvs_deck_patched.lylvs:145
+    Polygons (raw): 0 (flat)  0 (hierarchical)
+    Elapsed: 0.000s  Memory: 1137.00M
+"extract_devices" in: lvs_deck_patched.lylvs:151
+    Elapsed: 0.000s  Memory: 1137.00M
+"extract_devices" in: lvs_deck_patched.lylvs:152
+    Elapsed: 0.000s  Memory: 1138.00M
+"extract_devices" in: lvs_deck_patched.lylvs:153
+    Elapsed: 0.000s  Memory: 1138.00M
+"extract_devices" in: lvs_deck_patched.lylvs:156
+    Elapsed: 0.010s  Memory: 1138.00M
+"extract_devices" in: lvs_deck_patched.lylvs:157
+    Elapsed: 0.000s  Memory: 1138.00M
+"extract_devices" in: lvs_deck_patched.lylvs:158
+    Elapsed: 0.000s  Memory: 1138.00M
+"extract_devices" in: lvs_deck_patched.lylvs:159
+    Elapsed: 0.000s  Memory: 1138.00M
+"netlist" in: lvs_deck_patched.lylvs:199
+    Elapsed: 0.000s  Memory: 1138.00M
+Flatten layout cell (no schematic): VIA_L1M1_PR
+Flatten layout cell (no schematic): VIA_M2M3_PR
+Flatten layout cell (no schematic): VIA_M1M2_PR
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2111O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A211O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BOI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BO_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BO_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21BO_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A21O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A221O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A222OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A22O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A2BB2O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A311O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A31O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A32O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41OI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41OI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41OI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41O_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41O_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__A41O_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4BB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4BB_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4BB_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__AND4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFBUF_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFBUF_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFINV_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUFINV_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_12
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_6
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__BUF_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKBUF_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S15_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S15_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S18_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S18_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S25_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S25_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S50_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKDLYBUF4S50_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINVLP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINVLP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CLKINV_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_12
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_3
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_6
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DECAP_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFBBN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFBBN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFBBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFRTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFSTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DFXTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DIODE_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLCLKP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLCLKP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLCLKP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTN_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLRTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXBN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXBN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTN_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYGATE4SD1_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYGATE4SD2_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYGATE4SD3_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYMETAL6S2S_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYMETAL6S4S_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__DLYMETAL6S6S_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EBUFN_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EDFXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EDFXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVN_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__EINVP_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FAHCIN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FAHCON_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FAH_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FA_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FA_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FA_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__FILL_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__HA_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__HA_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__HA_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_12
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_6
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_BLEEDER_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_12
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_6
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_16
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MACRO_SPARECELL
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__CONB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__INV_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MAJ3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MAJ3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2I_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2I_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2I_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX2_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX4_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__MUX4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND2_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4BB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4BB_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4BB_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NAND4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR2_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4BB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4BB_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4BB_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__NOR4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2111A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O211A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21AI_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BAI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BAI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BAI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BA_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O21BA_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O221A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O22A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O2BB2A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311AI_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O311A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O31A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O32A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41AI_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41AI_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41AI_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41A_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41A_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__O41A_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_0
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4BB_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4BB_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4BB_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4B_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4B_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4B_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__OR4_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__PROBEC_P_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__PROBE_P_8
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFBBN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFBBN_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFBBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTN_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFRTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFSTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDFXTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDLCLKP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDLCLKP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SDLCLKP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXBP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXBP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXTP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXTP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__SEDFXTP_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAPVGND2_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAPVGND_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAP_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__TAP_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR3_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XNOR3_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR2_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR2_4
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR3_1
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR3_2
+Flatten schematic circuit (no layout): SKY130_FD_SC_HD__XOR3_4
+Writing netlist: /tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/lvs_extracted.cir ..
+Writing LVS database: /tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/lvs_report.lyrdb ..
+Total elapsed: 0.330s  Memory: 1147.00M
+INFO : Congratulations! Netlists match.
+
+=== stderr ===

alu_w4_2ops_sky130_50mhz/flow/lvs_cleaned.gds.gz

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:f2c2b0f24e50ef6c58429fa71b746fdb89457f6465b39636d18be00ad54709ce
+size 10565

alu_w4_2ops_sky130_50mhz/flow/lvs_deck_patched.lylvs

@@ -0,0 +1,295 @@
+<?xml version="1.0" encoding="utf-8"?>
+<klayout-macro>
+ <description/>
+ <version/>
+ <category>lvs</category>
+ <prolog/>
+ <epilog/>
+ <doc/>
+ <autorun>false</autorun>
+ <autorun-early>false</autorun-early>
+ <shortcut/>
+ <show-in-menu>true</show-in-menu>
+ <group-name>lvs_scripts</group-name>
+ <menu-path>tools_menu.lvs.end</menu-path>
+ <interpreter>dsl</interpreter>
+ <dsl-interpreter-name>lvs-dsl-xml</dsl-interpreter-name>
+ <text>#
+# Extraction for SKY130
+#
+############################
+
+# optionnal for a batch launch :   klayout -b -rd in_gds=my_layout.gds -rd report_file=my_report.lyrdb -rd cdl_file=reference_netlist.cir -rd target_netlist=extracted_netlist.cir -r sky130.lylvs
+if $in_gds
+  source($in_gds)
+end
+
+if $report_file
+  report_lvs($report_file)
+else
+  report_lvs("lvs_report.lvsdb")
+end
+
+if $cdl_file
+#reference netlist
+   schematic($cdl_file)
+else 
+   schematic("sky130hd.cdl")
+end
+
+# true: use net names instead of numbers
+# false: use numbers for nets
+spice_with_net_names = true
+
+# true: put in comments with details
+# false: no comments
+spice_with_comments = false
+
+if $target_netlist
+  target_netlist($target_netlist)
+else
+   # target_netlist("netlist.cir", write_spice(spice_with_net_names, spice_with_comments), "The netlist comment goes here.") 
+   target_netlist(File.join(File.dirname(RBA::CellView::active.filename), source.cell_name+"_extracted.cir"), write_spice(spice_with_net_names, spice_with_comments),  "Extracted by KLayout on : #{Time.now.strftime("%d/%m/%Y %H:%M")}")
+end
+
+# Hierarchical mode
+deep
+# Use 4 CPU cores
+threads(4)
+# Print details
+verbose(true)
+
+
+# layers definitions
+########################
+BOUND  = polygons(235, 4)
+DNWELL  = polygons(64, 18)
+PWRES  = polygons(64, 13)
+NWELL  = polygons(64, 20)
+NWELLTXT  = input(64, 5)
+NWELLPIN  = polygons(64, 16)
+SUBTXT  = input(122, 5)
+SUBPIN  = input(64, 59)
+DIFF  = polygons(65, 20)
+TAP  = polygons(65, 44)
+PSDM  = polygons(94, 20)
+NSDM  = polygons(93, 44)
+LVTN  = polygons(125, 44)
+HVTR  = polygons(18, 20)
+HVTP  = polygons(78, 44)
+SONOS  = polygons(80, 20)
+COREID  = polygons(81, 2)
+STDCELL  = polygons(81, 4)
+NPNID  = polygons(82, 20)
+PNPID  = polygons(82, 44)
+RPM  = polygons(86, 20)
+URPM  = polygons(79, 20)
+LDNTM  = polygons(11, 44)
+HVNTM  = polygons(125, 20)
+POLY  = polygons(66, 20)
+POLYTXT  = input(66, 5)
+POLYPIN  = polygons(66, 16)
+HVI  = polygons(75, 20)
+LICON  = polygons(66, 44)
+NPC  = polygons(95, 20)
+DIFFRES  = polygons(65, 13)
+POLYRES  = polygons(66, 13)
+POLYSHO  = polygons(66, 15)
+DIODE  = polygons(81, 23)
+LI  = polygons(67, 20)
+LITXT  = input(67, 5)
+LIPIN  = polygons(67, 16)
+LIRES  = polygons(67, 13)
+MCON  = polygons(67, 44)
+MET1  = polygons(68, 20)
+MET1TXT  = input(68, 5)
+MET1PIN  = polygons(68, 16)
+MET1RES  = polygons(68, 13)
+VIA1  = polygons(68, 44)
+MET2  = polygons(69, 20)
+MET2TXT  = input(69, 5)
+MET2PIN  = polygons(69, 16)
+MET2RES  = polygons(69, 13)
+VIA2  = polygons(69, 44)
+MET3  = polygons(70, 20)
+MET3TXT  = input(70, 5)
+MET3PIN  = polygons(70, 16)
+MET3RES  = polygons(70, 13)
+VIA3  = polygons(70, 44)
+MET4  = polygons(71, 20)
+MET4TXT  = input(71, 5)
+MET4PIN  = polygons(71, 16)
+MET4RES  = polygons(71, 13)
+VIA4  = polygons(71, 44)
+MET5  = polygons(72, 20)
+MET5TXT  = input(72, 5)
+MET5PIN  = polygons(72, 16)
+MET5RES  = polygons(72, 13)
+RDL  = polygons(74, 20)
+RDLTXT  = input(74, 5)
+RDLPIN  = polygons(74, 16)
+GLASS  = polygons(76, 20)
+CAPM  = polygons(89, 44)
+CAPM2  = polygons(97, 44)
+LOWTAPD  = polygons(81, 14)
+FILLOBSM1  = polygons(62, 24)
+FILLOBSM2  = polygons(105, 52)
+FILLOBSM3  = polygons(107, 24)
+FILLOBSM4  = polygons(112, 4)
+NCM = polygons(92, 44)
+
+# Bulk layer for terminal provisioning
+SUB = polygons(236, 0)
+# SUB = polygon_layer
+
+# Computed layers
+PDIFF = DIFF &amp; NWELL &amp; PSDM
+NTAP = TAP &amp; NWELL &amp; NSDM
+PGATE = PDIFF &amp; POLY
+PSD = PDIFF - PGATE
+STD_PGATE = PGATE - HVTP - NCM - HVI
+HVT_PGATE = PGATE &amp; HVTP - NCM - HVI
+HV5_PGATE = PGATE - HVTP - NCM &amp; HVI
+  
+NDIFF = DIFF - NWELL &amp; NSDM
+PTAP = TAP - NWELL &amp; PSDM
+NGATE = NDIFF &amp; POLY
+NSD = NDIFF - NGATE
+STD_NGATE = NGATE - NCM - LVTN - HVI
+LVT_NGATE = NGATE - NCM &amp; LVTN - HVI
+HV5_NGATE = NGATE - NCM - LVTN &amp; HVI
+HV5NA_NGATE = NGATE - NCM &amp; LVTN &amp; HVI
+
+# drawing to physical
+device_scaling(1000000)
+
+# PMOS transistor device extraction
+extract_devices(mos4("pfet_01v8"), { "SD" =&gt; PSD, "G" =&gt; STD_PGATE, "tS" =&gt; PSD, "tD" =&gt; PSD, "tG" =&gt; POLY, "W" =&gt; NWELL })
+extract_devices(mos4("pfet_01v8_hvt"), { "SD" =&gt; PSD, "G" =&gt; HVT_PGATE, "tS" =&gt; PSD, "tD" =&gt; PSD, "tG" =&gt; POLY, "W" =&gt; NWELL })
+extract_devices(mos4("pfet_g5v0d10v5"), { "SD" =&gt; PSD, "G" =&gt; HV5_PGATE, "tS" =&gt; PSD, "tD" =&gt; PSD, "tG" =&gt; POLY, "W" =&gt; NWELL })
+
+# NMOS transistor device extraction
+extract_devices(mos4("nfet_01v8"), { "SD" =&gt; NSD, "G" =&gt; STD_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
+extract_devices(mos4("nfet_01v8_lvt"), { "SD" =&gt; NSD, "G" =&gt; LVT_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
+extract_devices(mos4("nfet_g5v0d10v5"), { "SD" =&gt; NSD, "G" =&gt; HV5_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
+extract_devices(mos4("nfet_01v8_nvt"), { "SD" =&gt; NSD, "G" =&gt; HV5NA_NGATE, "tS" =&gt; NSD, "tD" =&gt; NSD, "tG" =&gt; POLY, "W" =&gt; SUB })
+
+
+# Define connectivity for netlist extraction
+
+# Inter-layer
+connect(SUB,  PTAP)
+connect(NWELL,  NTAP)
+connect(LICON,   PTAP)
+connect(LICON,   NTAP)
+connect(PSD,    LICON)
+connect(NSD,    LICON)
+connect(POLY,   LICON)
+connect(LICON,   LI)
+connect(LI, MCON)
+connect(MCON,   MET1)
+connect(MET1,VIA1)
+connect(VIA1,   MET2)
+connect(MET2, VIA2)
+connect(VIA2,   MET3)
+connect(MET3, VIA3)
+connect(VIA3,   MET4)
+connect(MET4, VIA4)
+connect(VIA4,   MET5)
+# Attaching labels
+connect(SUB, SUBTXT)
+connect(SUB, SUBPIN)
+connect(NWELL, NWELLTXT)
+connect(POLY, POLYTXT)
+connect(LI, LITXT)
+connect(MET1, MET1TXT)
+connect(MET2, MET2TXT)
+connect(MET3, MET3TXT)
+connect(MET4, MET4TXT)
+connect(MET5, MET5TXT)
+
+# Global
+connect_global(SUB, "VNB")
+
+# Actually performs the extraction
+netlist # ... not really required
+
+# Flatten cells which are present in one netlist only
+align
+
+# Flat LVS: flatten all cells to transistor level.
+# This avoids hierarchical port identification issues where
+# KLayout misses output pins on cells whose LI shapes are
+# only on the PIN datatype (67/16) not DRAWING (67/20).
+netlist.flatten_circuit("*")
+schematic.flatten_circuit("*")
+
+netlist.make_top_level_pins
+netlist.combine_devices
+netlist.purge
+schematic.combine_devices
+schematic.purge
+
+# Tolerances for the devices extracted parameters
+#  tolerance(device_class_name, parameter_name [, :absolute =&gt; absolute_tolerance] [, :relative =&gt; relative_tolerance])
+tolerance("pfet_01v8", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("pfet_01v8", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("pfet_01v8_hvt", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("pfet_01v8_hvt", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("nfet_01v8", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("nfet_01v8", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("nfet_01v8_lvt", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+tolerance("nfet_01v8_lvt", "L", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
+
+# NangateOpenCellLibrary Digital gates input equivalence :
+equivalent_pins("*AND2_1", "A", "B")
+equivalent_pins("*AND2_2", "A", "B")
+equivalent_pins("*AND2_4", "A", "B")
+equivalent_pins("*AND3_1", "A", "B", "C")
+equivalent_pins("*AND3_2", "A", "B", "C")
+equivalent_pins("*AND3_4", "A", "B", "C")
+equivalent_pins("*AND4_1", "A", "B", "C", "D")
+equivalent_pins("*AND4_2", "A", "B", "C", "D")
+equivalent_pins("*AND4_4", "A", "B", "C", "D")
+equivalent_pins("*NAND2_1", "A", "B")
+equivalent_pins("*NAND2_2", "A", "B")
+equivalent_pins("*NAND2_4", "A", "B")
+equivalent_pins("*NAND3_1", "A", "B", "C")
+equivalent_pins("*NAND3_2", "A", "B", "C")
+equivalent_pins("*NAND3_4", "A", "B", "C")
+equivalent_pins("*NAND4_X1", "A", "B", "C", "D")
+equivalent_pins("*NAND4_2", "A", "B", "C", "D")
+equivalent_pins("*NAND4_4", "A", "B", "C", "D")
+equivalent_pins("*OR2_1", "A", "B")
+equivalent_pins("*OR2_2", "A", "B")
+equivalent_pins("*OR2_4", "A", "B")
+equivalent_pins("*OR3_1", "A", "B", "C")
+equivalent_pins("*OR3_2", "A", "B", "C")
+equivalent_pins("*OR3_4", "A", "B", "C")
+equivalent_pins("*OR4_1", "A", "B", "C", "D")
+equivalent_pins("*OR4_2", "A", "B", "C", "D")
+equivalent_pins("*OR4_4", "A", "B", "C", "D")
+equivalent_pins("*NOR2_1", "A", "B")
+equivalent_pins("*NOR2_2", "A", "B")
+equivalent_pins("*NOR2_4", "A", "B")
+equivalent_pins("*NOR3_1", "A", "B", "C")
+equivalent_pins("*NOR3_2", "A", "B", "C")
+equivalent_pins("*NOR3_4", "A", "B", "C")
+equivalent_pins("*NOR4_1", "A", "B", "C", "D")
+equivalent_pins("*NOR4_2", "A", "B", "C", "D")
+equivalent_pins("*NOR4_4", "A", "B", "C", "D")
+equivalent_pins("*XOR2_1", "A", "B")
+equivalent_pins("*XOR2_2", "A", "B")
+equivalent_pins("*XNOR2_1", "A", "B")
+equivalent_pins("*XNOR2_2", "A", "B")
+
+#max_res(1000000)
+#min_caps(1e-15)
+
+if ! compare 
+  #raise "ERROR : Netlists don't match"
+  puts "ERROR : Netlists don't match"
+else
+  puts "INFO : Congratulations! Netlists match."
+end</text>
+</klayout-macro>

alu_w4_2ops_sky130_50mhz/flow/lvs_report.lyrdb

@@ -0,0 +1,694 @@
+#%lvsdb-klayout
+J(
+ W(alu_w4_2ops)
+ U(0.001)
+ L(l3 '64/20')
+ L(l29 '64/5')
+ L(l27)
+ L(l28 '64/59')
+ L(l4 '66/20')
+ L(l30)
+ L(l15 '66/44')
+ L(l16 '67/20')
+ L(l31 '67/5')
+ L(l17 '67/44')
+ L(l18 '68/20')
+ L(l32 '68/5')
+ L(l19 '68/44')
+ L(l20 '69/20')
+ L(l33)
+ L(l21 '69/44')
+ L(l22 '70/20')
+ L(l34 '70/5')
+ L(l23)
+ L(l24)
+ L(l35)
+ L(l25)
+ L(l26)
+ L(l36)
+ L(l9 '236/0')
+ L(l14)
+ L(l2)
+ L(l13)
+ L(l8)
+ C(l3 l3 l29 l14)
+ C(l29 l3 l29)
+ C(l27 l27 l9)
+ C(l28 l28 l9)
+ C(l4 l4 l30 l15)
+ C(l30 l4 l30)
+ C(l15 l4 l15 l16 l14 l2 l13 l8)
+ C(l16 l15 l16 l31 l17)
+ C(l31 l16 l31)
+ C(l17 l16 l17 l18)
+ C(l18 l17 l18 l32 l19)
+ C(l32 l18 l32)
+ C(l19 l18 l19 l20)
+ C(l20 l19 l20 l33 l21)
+ C(l33 l20 l33)
+ C(l21 l20 l21 l22)
+ C(l22 l21 l22 l34 l23)
+ C(l34 l22 l34)
+ C(l23 l22 l23 l24)
+ C(l24 l23 l24 l35 l25)
+ C(l35 l24 l35)
+ C(l25 l24 l25 l26)
+ C(l26 l25 l26 l36)
+ C(l36 l26 l36)
+ C(l9 l27 l28 l9 l13)
+ C(l14 l3 l15 l14)
+ C(l2 l15 l2)
+ C(l13 l15 l9 l13)
+ C(l8 l15 l8)
+ G(l9 VNB)
+ K(pfet_01v8 MOS4)
+ K(pfet_01v8_hvt MOS4)
+ K(pfet_g5v0d10v5 MOS4)
+ K(nfet_01v8 MOS4)
+ K(nfet_01v8_lvt MOS4)
+ K(nfet_g5v0d10v5 MOS4)
+ K(nfet_01v8_nvt MOS4)
+ D(D$pfet_01v8_hvt pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l2 (75 -210) (0 420) (75 0) (0 580) (260 0) (0 -1000))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$1 pfet_01v8_hvt
+  T(S
+   Q(l2 (-410 -500) (0 420) (75 0) (0 580) (260 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$2 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (265 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$3 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (300 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$4 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$5 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$6 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$7 pfet_01v8_hvt
+  T(S
+   R(l2 (-375 -500) (300 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (330 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$8 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$9 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -500) (210 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (280 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$10 pfet_01v8_hvt
+  T(S
+   Q(l2 (-490 -210) (0 1000) (340 0) (0 -580) (75 0) (0 -420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (280 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$11 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   Q(l2 (75 -500) (0 1000) (340 0) (0 -580) (75 0) (0 -420))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$12 pfet_01v8_hvt
+  T(S
+   R(l2 (-375 -500) (300 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (270 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$13 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -500) (270 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (730 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$14 pfet_01v8_hvt
+  T(S
+   R(l2 (-805 -500) (730 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$15 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -500) (210 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (330 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$16 pfet_01v8_hvt
+  T(S
+   R(l2 (-405 -500) (330 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (360 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$17 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (210 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$18 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (270 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$19 pfet_01v8_hvt
+  T(S
+   R(l2 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (75 -210) (210 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$20 pfet_01v8_hvt
+  T(S
+   Q(l2 (165 -430) (0 220) (-90 0) (0 420) (130 0) (0 360) (435 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l2 (-285 -210) (210 420))
+  )
+  T(B
+   R(l3 (-75 -210) (150 420))
+  )
+ )
+ D(D$pfet_01v8_hvt$21 pfet_01v8_hvt
+  T(S
+   Q(l2 (-550 -500) (0 220) (-90 0) (0 420) (130 0) (0 360) (435 0) (0 -1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (365 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$22 pfet_01v8_hvt
+  T(S
+   R(l2 (-335 -500) (260 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (210 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$pfet_01v8_hvt$23 pfet_01v8_hvt
+  T(S
+   R(l2 (-285 -500) (210 1000))
+  )
+  T(G
+   R(l4 (-75 -500) (150 1000))
+  )
+  T(D
+   R(l2 (75 -500) (260 1000))
+  )
+  T(B
+   R(l3 (-75 -500) (150 1000))
+  )
+ )
+ D(D$nfet_01v8 nfet_01v8
+  T(S
+   Q(l8 (150 -440) (0 230) (-75 0) (0 420) (335 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (-335 -210) (260 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$1 nfet_01v8
+  T(S
+   Q(l8 (-335 -325) (0 230) (-75 0) (0 420) (335 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$2 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (260 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$3 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$4 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$5 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (770 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$6 nfet_01v8
+  T(S
+   R(l8 (-845 -325) (770 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (320 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$7 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (330 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$8 nfet_01v8
+  T(S
+   R(l8 (-405 -325) (330 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$9 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (265 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$10 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   Q(l8 (75 -325) (0 650) (335 0) (0 -420) (-75 0) (0 -230))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$11 nfet_01v8
+  T(S
+   Q(l8 (-410 -440) (0 650) (335 0) (0 -420) (-75 0) (0 -230))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (260 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$12 nfet_01v8
+  T(S
+   R(l8 (-345 -325) (270 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (300 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$13 nfet_01v8
+  T(S
+   R(l8 (-335 -325) (260 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (210 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$14 nfet_01v8
+  T(S
+   R(l8 (-285 -325) (210 650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (270 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+ D(D$nfet_01v8$15 nfet_01v8
+  T(S
+   R(l8 (-335 -210) (260 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (210 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$16 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (270 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$17 nfet_01v8
+  T(S
+   R(l8 (-345 -210) (270 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   R(l8 (75 -210) (210 420))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$18 nfet_01v8
+  T(S
+   R(l8 (-285 -210) (210 420))
+  )
+  T(G
+   R(l4 (-75 -210) (150 420))
+  )
+  T(D
+   Q(l8 (75 -210) (0 420) (315 0) (0 230) (250 0) (0 -650))
+  )
+  T(B
+   R(l9 (-75 -210) (150 420))
+  )
+ )
+ D(D$nfet_01v8$19 nfet_01v8
+  T(S
+   Q(l8 (-640 -325) (0 420) (315 0) (0 230) (250 0) (0 -650))
+  )
+  T(G
+   R(l4 (-75 -325) (150 650))
+  )
+  T(D
+   R(l8 (75 -325) (365 650))
+  )
+  T(B
+   R(l9 (-75 -325) (150 650))
+  )
+ )
+)
+H(
+ K(PFET_01V8_HVT MOS4)
+ K(NFET_01V8 MOS4)
+ K(RES RES)
+)
+Z(
+)

alu_w4_2ops_sky130_50mhz/flow/netlist.v

@@ -0,0 +1,116 @@
+/* Generated by Yosys 0.46 (git sha1 e97731b9dda91fa5fa53ed87df7c34163ba59a41, clang++ 17.0.6 -fPIC -O3) */
+
+module alu_w4_2ops(a, b, sel, result);
+  wire _00_;
+  wire _01_;
+  wire _02_;
+  wire _03_;
+  wire _04_;
+  wire _05_;
+  wire _06_;
+  wire _07_;
+  wire _08_;
+  wire _09_;
+  wire _10_;
+  wire _11_;
+  wire _12_;
+  input [3:0] a;
+  wire [3:0] a;
+  input [3:0] b;
+  wire [3:0] b;
+  output [3:0] result;
+  wire [3:0] result;
+  input sel;
+  wire sel;
+  sky130_fd_sc_hd__nand2b_1 _13_ (
+    .A_N(a[0]),
+    .B(b[0]),
+    .Y(_00_)
+  );
+  sky130_fd_sc_hd__xor2_1 _14_ (
+    .A(b[0]),
+    .B(a[0]),
+    .X(result[0])
+  );
+  sky130_fd_sc_hd__nand2_1 _15_ (
+    .A(b[1]),
+    .B(b[0]),
+    .Y(_01_)
+  );
+  sky130_fd_sc_hd__o21ba_1 _16_ (
+    .A1(b[1]),
+    .A2(b[0]),
+    .B1_N(sel),
+    .X(_02_)
+  );
+  sky130_fd_sc_hd__a22oi_1 _17_ (
+    .A1(b[1]),
+    .A2(sel),
+    .B1(_01_),
+    .B2(_02_),
+    .Y(_03_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _18_ (
+    .A(a[1]),
+    .B(_03_),
+    .Y(_04_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _19_ (
+    .A(_00_),
+    .B(_04_),
+    .Y(result[1])
+  );
+  sky130_fd_sc_hd__maj3_1 _20_ (
+    .A(a[1]),
+    .B(_00_),
+    .C(_03_),
+    .X(_05_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _21_ (
+    .A(b[2]),
+    .B(_02_),
+    .Y(_06_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _22_ (
+    .A(a[2]),
+    .B(_06_),
+    .Y(_07_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _23_ (
+    .A(_05_),
+    .B(_07_),
+    .Y(result[2])
+  );
+  sky130_fd_sc_hd__maj3_1 _24_ (
+    .A(a[2]),
+    .B(_05_),
+    .C(_06_),
+    .X(_08_)
+  );
+  sky130_fd_sc_hd__nor3_1 _25_ (
+    .A(b[1]),
+    .B(b[2]),
+    .C(b[0]),
+    .Y(_09_)
+  );
+  sky130_fd_sc_hd__nor2_1 _26_ (
+    .A(sel),
+    .B(_09_),
+    .Y(_10_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _27_ (
+    .A(b[3]),
+    .B(a[3]),
+    .Y(_11_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _28_ (
+    .A(_10_),
+    .B(_11_),
+    .Y(_12_)
+  );
+  sky130_fd_sc_hd__xnor2_1 _29_ (
+    .A(_08_),
+    .B(_12_),
+    .Y(result[3])
+  );
+endmodule

alu_w4_2ops_sky130_50mhz/flow/write_cdl.tcl

@@ -0,0 +1,4 @@
+read_lef /nix/store/sjh17jnslbv9d60450qybp1ajym2fb83-source/flow/platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
+read_lef /nix/store/sjh17jnslbv9d60450qybp1ajym2fb83-source/flow/platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
+read_def /tmp/zyphar_pnr_973323.def
+write_cdl -masters /nix/store/sjh17jnslbv9d60450qybp1ajym2fb83-source/flow/platforms/sky130hd/cdl/sky130hd.cdl /tmp/datagen_output/alu_w4_2ops_sky130_50mhz/flow/design_only.cdl