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Xenn007
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synth-layout-v1

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Other
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1B<n<10B
Tags:
eda
chip-design
vlsi
synthesis
place-and-route
drc
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  1. alu_w4_3ops_sky130_1000mhz/flow/alu_w4_3ops.gds.gz +3 -0
  2. alu_w4_3ops_sky130_1000mhz/flow/alu_w4_3ops.spef.gz +3 -0
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  5. alu_w4_3ops_sky130_1000mhz/flow/lvs_reference.cdl.gz +3 -0
  6. alu_w4_3ops_sky130_1000mhz/flow/output.def.gz +3 -0
  7. alu_w4_3ops_sky130_100mhz/flow/alu_w4_3ops.gds.gz +3 -0
  8. alu_w4_3ops_sky130_100mhz/flow/alu_w4_3ops.spef.gz +3 -0
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  13. alu_w4_3ops_sky130_200mhz/flow/alu_w4_3ops.gds.gz +3 -0
  14. alu_w4_3ops_sky130_200mhz/flow/alu_w4_3ops.spef.gz +3 -0
  15. alu_w4_3ops_sky130_200mhz/flow/design_only.cdl.gz +3 -0
  16. alu_w4_3ops_sky130_200mhz/flow/lvs_cleaned.gds.gz +3 -0
  17. alu_w4_3ops_sky130_200mhz/flow/lvs_reference.cdl.gz +3 -0
  18. alu_w4_3ops_sky130_200mhz/flow/output.def.gz +3 -0
  19. alu_w4_3ops_sky130_500mhz/flow/alu_w4_3ops.gds.gz +3 -0
  20. alu_w4_3ops_sky130_500mhz/flow/alu_w4_3ops.spef.gz +3 -0
  21. alu_w4_3ops_sky130_500mhz/flow/design_only.cdl.gz +3 -0
  22. alu_w4_3ops_sky130_500mhz/flow/lvs_cleaned.gds.gz +3 -0
  23. alu_w4_3ops_sky130_500mhz/flow/lvs_reference.cdl.gz +3 -0
  24. alu_w4_3ops_sky130_500mhz/flow/output.def.gz +3 -0
  25. alu_w4_3ops_sky130_50mhz/flow/design_only.cdl.gz +3 -0
  26. alu_w4_3ops_sky130_50mhz/flow/lvs_cleaned.gds.gz +3 -0
  27. alu_w8_2ops_sky130_100mhz/flow/alu_w8_2ops.spef.gz +3 -0
  28. alu_w8_2ops_sky130_50mhz/flow/alu_w8_2ops.gds.gz +3 -0
  29. alu_w8_2ops_sky130_50mhz/flow/alu_w8_2ops.spef.gz +3 -0
  30. alu_w8_2ops_sky130_50mhz/flow/design_only.cdl.gz +3 -0
  31. alu_w8_2ops_sky130_50mhz/flow/lvs_cleaned.gds.gz +3 -0
  32. alu_w8_2ops_sky130_50mhz/flow/lvs_reference.cdl.gz +3 -0
  33. alu_w8_2ops_sky130_50mhz/flow/output.def.gz +3 -0
  34. shiftreg_w8_d8_sipo_sky130_1000mhz/flow/design_only.cdl.gz +3 -0
  35. shiftreg_w8_d8_siso_sky130_100mhz/flow/design_only.cdl.gz +3 -0
  36. shiftreg_w8_d8_siso_sky130_100mhz/flow/lvs_cleaned.gds.gz +3 -0
  37. shiftreg_w8_d8_siso_sky130_100mhz/flow/lvs_reference.cdl.gz +3 -0
  38. shiftreg_w8_d8_siso_sky130_100mhz/flow/output.def.gz +3 -0
  39. shiftreg_w8_d8_siso_sky130_100mhz/flow/shiftreg_w8_d8_siso.gds.gz +3 -0
  40. shiftreg_w8_d8_siso_sky130_100mhz/flow/shiftreg_w8_d8_siso.spef.gz +3 -0
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