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Datasets:
SAIFIINDUSTRIES
/
verilog_data-2
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xet
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f834131
verilog_data-2
/
abdelazeem201_Cadence-RTL-to-GDSII-Flow
1 contributor
History:
1 commit
SAIFIINDUSTRIES
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a7407e6
verified
6 days ago
Constraints
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Equivalence_checking
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LIB
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RTL
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STA
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Simulation
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Synthesis
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gate_level_simulation
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physical_design
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README.md
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10.5 kB
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6 days ago
