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Datasets:
SAIFIINDUSTRIES
/
verilog_data-2
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0
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Files
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xet
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a088a35
verilog_data-2
/
MasLiang_CNN-On-FPGA
/
verilog
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add Batch 1 with 10 repos
8dc19e4
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6 days ago
Conv_unsign_sign.v
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Layer1_Conv_Top.v
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Layer1_Pool_Top.v
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Layer2_Conv_Top.v
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Layer2_Pool_Top.v
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Layer3_Conv_Top.v
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Layer3_Pool_Top.v
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conv3_out_buffer.v
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ful_conn.v
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maxpool.v
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maxpool_one_clk.v
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pic_in.v
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pool1_out_buffer.v
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pool2_out_buffer.v
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top.v
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3.13 kB
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