Hugging Face
Models
Datasets
Spaces
Buckets
new
Docs
Enterprise
Pricing
Website
Tasks
HuggingChat
Collections
Languages
Organizations
Community
Blog
Posts
Daily Papers
Hardware
Learn
Discord
Forum
GitHub
Solutions
Team & Enterprise
Hugging Face PRO
Enterprise Support
Inference Providers
Inference Endpoints
Storage Buckets
Log In
Sign Up
Datasets:
SAIFIINDUSTRIES
/
verilog_data-2
like
0
Dataset card
Files
Files and versions
xet
Community
8dc19e4
verilog_data-2
/
ultraembedded_openlogicbit
/
core
/
capture
84 kB
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add Batch 2 with 10 repos
1893362
verified
5 days ago
capture_rle.v
Safe
5.64 kB
Add Batch 2 with 10 repos
5 days ago
capture_rle_cdc.v
Safe
9.1 kB
Add Batch 2 with 10 repos
5 days ago
logic_capture.v
Safe
21.7 kB
Add Batch 2 with 10 repos
5 days ago
logic_capture_defs.v
Safe
5.83 kB
Add Batch 2 with 10 repos
5 days ago
logic_capture_fifo.v
Safe
4.78 kB
Add Batch 2 with 10 repos
5 days ago
logic_capture_mem.v
Safe
11.3 kB
Add Batch 2 with 10 repos
5 days ago
logic_capture_mem_axi.v
Safe
9.82 kB
Add Batch 2 with 10 repos
5 days ago
logic_capture_mem_axi_axi.v
Safe
7.54 kB
Add Batch 2 with 10 repos
5 days ago
logic_capture_mem_fifo_ram.v
Safe
4.99 kB
Add Batch 2 with 10 repos
5 days ago
logic_capture_mem_track_fifo.v
Safe
3.33 kB
Add Batch 2 with 10 repos
5 days ago
