{
  "name": "v2_mesh0",
  "layout": "merged",
  "clusters": [[1, 0], [1, 1], [2, 1], [1, 2], [2, 2], [1, 3]],
  "vectors": [[2, 0], [2, 3]],
  "ports": [[0, 1], [0, 2]],
  "accumulators": [],
  "ncol": 2,
  "nrow": 2,
  "ctrl_base": "0x400800000",
  "mem_base": "0x0",
  "orc_base": "0x0",
  "orchestrator": "host",
  "quant_bit": 33,
  "blay_bit": 32,
  "mem_words": 134217728,
  "transport": "jtag",
  "features": [],
  "tiles": 512,
  "l1_a": 512,
  "l1_b": 512,
  "cu_version": 3,
  "stage_flits": 128,
  "l1_banks": 2,
  "inst_depth": 512,
  "source": "HAND-WRITTEN, not from gen_board.py. TOPOLOGY read off src/synth_top/maps/mesh_2x2_6+2.txt, which is the map multimesh v3's mesh_0/2/3 instantiate as ktpu_ship_2x2_6c2v_1m. CAPACITIES and inst_depth READ BACK FROM THE CARD's CU_CAPS on 2026-08-13 (inst_depth 512, buffers 2, cu_version 3), not from a synth log. ADDRESS MAP is the v2 bitstream's: ctrl 0x400800000, mesh_0 DRAM at 0. Exists to run the OLD stack against the same silicon as the new compiler, as a cross-check."
}