{
  "name": "singlemesh_2x2",
  "layout": "split",
  "clusters": [[1, 1], [1, 2]],
  "accumulators": [[2, 1], [2, 2]],
  "ports": [[0, 1], [0, 2]],
  "vectors": [[1, 0], [2, 0], [1, 3], [2, 3]],
  "ncol": 2,
  "nrow": 2,
  "ctrl_base": "0x400800000",
  "mem_base": "0x0",
  "orchestrator": "host",
  "orc_base": "0x0",
  "quant_bit": null,
  "blay_bit": null,
  "stage_flits": 128,
  "inst_depth": 32,
  "mem_words": 134217728,
  "tiles": 256,
  "l1_a": 32,
  "l1_b": 32,
  "l1_banks": 2,
  "mem_ports": 2,
  "transport": "xdma",
  "source": "Coordinates read off the OOC synthesis log of the mesh IP, JTAG-DMA-test.runs/singlemesh_ktpu_mesh_2x2_0_0_synth_1/runme.log (run 2026-08-10 00:34): mx_cluster_cu MGR=(1,1) ACU=(2,1) MEM=(0,1) and MGR=(1,2) ACU=(2,2) MEM=(0,2). Windows read off singlemesh.bd's own address_segments, not off the script that set them: jtag_axi_0/Data and xdma_0/M_AXI each carry SEG_ktpu_mesh_2x2_0_reg0 at 0x0_0000_0000 range 4G and SEG_ktpu_mesh_2x2_0_reg0_1 at 0x4_0080_0000 range 64K. Every xdma_0/M_AXI_LITE segment is is_excluded=TRUE, so the \\user character device reaches nothing of ours and control registers go over h2c_0/c2h_0 like everything else. quant_bit is null because S_AXI_MEM is ranged 4G: a host master cannot present address bits 33:32, so mag.v's quantise marker (mag.v s565) is unreachable and a pre-quantised upload must be refused rather than landing FP16 in a region sized for MXFP7. Widening that segment to 16G makes the bits 33 and 32. orchestrator is host because no synth_top mesh instantiates main_orch -- mag.v s198 wires S_AXI_CTRL straight to the agent. The COMPUTE CAPACITIES come from the same log: mx_cluster_node bound TILES=256 GA=32 GB=32, and kohaku_sdpram DEPTH=32 WIDTH=928 confirms the L1 depth. bench.py's constants describe the CURRENT RTL (512/128/256) and over-running any of them is silent -- measured on this card, planning 128x64x128 against 512/128/256 put 15,440 of 16,384 elements past 10% error with every gating check passing, and re-planning the same shape against 256/32/32 gave p50 1.71e-4 with 0 elements over 10%. STAGE_FLITS=128, INST_DEPTH=32 and MEM_PORTS=2 were checked in the same log and match. VERIFIED ON HARDWARE 2026-08-10 over JTAG: CAPS, STATUS, both cluster coordinates, block writes through S_AXI_MEM, and two matmuls end to end."
}