{
  "name": "ship_2x2",
  "layout": "merged",
  "clusters": [
    [
      1,
      1
    ],
    [
      2,
      1
    ],
    [
      1,
      2
    ],
    [
      2,
      2
    ]
  ],
  "vectors": [
    [
      1,
      0
    ],
    [
      2,
      0
    ],
    [
      3,
      1
    ],
    [
      3,
      2
    ]
  ],
  "ports": [
    [
      0,
      1
    ],
    [
      0,
      2
    ]
  ],
  "accumulators": [],
  "ncol": 2,
  "nrow": 2,
  "ctrl_base": "0x400800000",
  "mem_base": "0x0",
  "orc_base": "0x0",
  "orchestrator": "host",
  "quant_bit": null,
  "blay_bit": null,
  "mem_words": 134217728,
  "transport": "xdma",
  "features": [],
  "tiles": 256,
  "l1_a": 32,
  "l1_b": 32,
  "cu_version": 2,
  "stage_flits": 128,
  "l1_banks": 2,
  "inst_depth": 32,
  "source": "GENERATED by scripts/py/gen_board.py -- do not hand-edit. TOPOLOGY (coordinates, node types, ports, grid) from src/synth_top/maps/mesh_2x2_4cu4vec.txt, the same map synthesis consumed. CAPACITIES and CU_VERSION from C:\\Users\\apoll\\AppData\\Local\\Temp\\ktpu-ship-v2\\ktpu_ship_2x2.log, which elaborated top 'ktpu_ship_2x2' at 328.8 MHz -- these describe THAT BUILD and rot the moment another is made. ADDRESS MAP (ctrl_base, mem_base, quantise bits, orchestrator) passed in on the command line: they come from a block design nothing in this repo can read, so they are the least verifiable fields here. CAPACITY DRIFT vs the compiler: l1_a is 32 here and 128 in bench.py; l1_b is 32 here and 256 in bench.py; tiles is 256 here and 512 in bench.py. NOT VERIFIED AGAINST HARDWARE -- run `run_fpga.py --probe` and check the node sweep."
}