{
  "name": "multimesh_v65",
  "design": "multimesh_v65",
  "transport": "jtag",
  "meshes": 4,
  "vco_mhz": 1200,
  "wizard_outputs": {
    "noc":   {"index": 0, "nominal_mhz": 300},
    "mat2x": {"index": 1, "nominal_mhz": 600},
    "vec":   {"index": 2, "nominal_mhz": 300},
    "mag":   {"index": 3, "nominal_mhz": 300}
  },
  "profiles": {
    "low":  {"noc": 100, "mat2x": 200, "vec": 100, "mag": 100},
    "mid":  {"noc": 200, "mat2x": 400, "vec": 200, "mag": 200},
    "ship": {"noc": 300, "mat2x": 600, "vec": 300, "mag": 300}
  },
  "idle_profile": "low",
  "ctrl_stride": "0x10000",
  "ctrl_base": "0x800000",
  "wizard_base": "0x900000",
  "ddrctrl_base": "0x0",
  "ddrctrl_stride": "0x100000",
  "mem_window_shift": 40,
  "mem_window_offset": 1,
  "dram_mesh_shift": 36,
  "mem_words": 134217728,
  "agent_at_offset_zero": true,
  "max_burst_beats": 8,
  "bitstream": "C:/Users/apoll/Desktop/vivado/multimesh_v65/multimesh_v65.runs/impl_1/multimesh_v65_wrapper.bit",
  "probes": "C:/Users/apoll/Desktop/vivado/multimesh_v65/multimesh_v65.runs/impl_1/multimesh_v65_wrapper.ltx",
  "host_write_granule": 32,
  "host_write_replicates": true,
  "notes": "Derived from scripts/tcl/v6/50_addr_lit.tcl and verified on hardware 2026-08-20. Mesh N: ctrl at ctrl_base+N*stride, wizard DRP at wizard_base+N*stride, host memory window at (N+mem_window_offset)<<mem_window_shift, unit-issued global DRAM base at N<<dram_mesh_shift. Wizard ports are B6 Lite: SINGLE-BEAT 32-bit access only. S_AXI_CTRL wires straight to the agent block (no main_orch, MAG_BASE bit-28 select does not exist). JTAG manager: bursts over 16 beats wedge; 32-bit writes to the mem window land replicated across the full 32-byte word (strobes discarded), reads are 4-byte exact only single-beat. mat1x is mat2x/2 via BUFGCE_DIV, retuned only through mat2x."
}